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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id z49-v6si613248qtb.1.2018.08.14.11.54.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 14 Aug 2018 11:54:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45788 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpeSb-0003Uu-26 for patch@linaro.org; Tue, 14 Aug 2018 14:54:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52840) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdvp-0005Ce-AJ for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:22:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpduI-0006qd-R1 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:20:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44428) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpduI-0006nb-Ba for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:19:02 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpduF-0007NX-A2 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:18:59 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:18:07 +0100 Message-Id: <20180814181815.23348-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 37/45] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" One of the required effects of setting HCR_EL2.TGE is that when SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for all purposes except direct reads. That is, it effectively disables the MMU for the NS EL0/EL1 translation regime. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180724115950.17316-6-peter.maydell@linaro.org --- target/arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.18.0 diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b438e43a90..62f63e4e5b9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8396,6 +8396,14 @@ static inline bool regime_translation_disabled(CPUARMState *env, if (mmu_idx == ARMMMUIdx_S2NS) { return (env->cp15.hcr_el2 & HCR_VM) == 0; } + + if (env->cp15.hcr_el2 & HCR_TGE) { + /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ + if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { + return true; + } + } + return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; }