| Message ID | 20181002163556.10279-11-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement v8M stack limit checks | expand |
On 02/10/2018 18:35, Peter Maydell wrote: > Add v8M stack checks for the instructions in the T32 > "load/store single" encoding class: these are the > "immediate pre-indexed" and "immediate, post-indexed" > LDR and STR instructions. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/translate.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 3fb378a492d..65df8d6975c 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -11624,7 +11624,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) > imm = -imm; > /* Fall through. */ > case 0xf: /* Pre-increment. */ > - tcg_gen_addi_i32(addr, addr, imm); > writeback = 1; > break; > default: > @@ -11636,6 +11635,28 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) > > issinfo = writeback ? ISSInvalid : rs; > > + if (s->v8m_stackcheck && rn == 13 && writeback) { > + /* > + * Stackcheck. Here we know 'addr' is the current SP; > + * if imm is +ve we're moving SP up, else down. It is TIL +ve is a short form for positive, and -ve for negative. > + * UNKNOWN whether the limit check triggers when SP starts > + * below the limit and ends up above it; we chose to do so. > + */ > + if ((int32_t)imm < 0) { > + TCGv_i32 newsp = tcg_temp_new_i32(); > + > + tcg_gen_addi_i32(newsp, addr, imm); > + gen_helper_v8m_stackcheck(cpu_env, newsp); > + tcg_temp_free_i32(newsp); > + } else { > + gen_helper_v8m_stackcheck(cpu_env, addr); > + } > + } > + > + if (writeback && !postinc) { > + tcg_gen_addi_i32(addr, addr, imm); > + } > + > if (insn & (1 << 20)) { > /* Load. */ > tmp = tcg_temp_new_i32(); > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
On 10/2/18 11:35 AM, Peter Maydell wrote: > Add v8M stack checks for the instructions in the T32 > "load/store single" encoding class: these are the > "immediate pre-indexed" and "immediate, post-indexed" > LDR and STR instructions. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/translate.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/translate.c b/target/arm/translate.c index 3fb378a492d..65df8d6975c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11624,7 +11624,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) imm = -imm; /* Fall through. */ case 0xf: /* Pre-increment. */ - tcg_gen_addi_i32(addr, addr, imm); writeback = 1; break; default: @@ -11636,6 +11635,28 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) issinfo = writeback ? ISSInvalid : rs; + if (s->v8m_stackcheck && rn == 13 && writeback) { + /* + * Stackcheck. Here we know 'addr' is the current SP; + * if imm is +ve we're moving SP up, else down. It is + * UNKNOWN whether the limit check triggers when SP starts + * below the limit and ends up above it; we chose to do so. + */ + if ((int32_t)imm < 0) { + TCGv_i32 newsp = tcg_temp_new_i32(); + + tcg_gen_addi_i32(newsp, addr, imm); + gen_helper_v8m_stackcheck(cpu_env, newsp); + tcg_temp_free_i32(newsp); + } else { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + } + + if (writeback && !postinc) { + tcg_gen_addi_i32(addr, addr, imm); + } + if (insn & (1 << 20)) { /* Load. */ tmp = tcg_temp_new_i32();
Add v8M stack checks for the instructions in the T32 "load/store single" encoding class: these are the "immediate pre-indexed" and "immediate, post-indexed" LDR and STR instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/translate.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) -- 2.19.0