From patchwork Tue Oct 2 16:35:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 147999 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5372085lji; Tue, 2 Oct 2018 09:36:01 -0700 (PDT) X-Google-Smtp-Source: ACcGV631a35xfFviy5gtmuJJLjm7uzmGG96v6aEKFs8LUcgdBgP9Q1vYFo0AkBxuqsPibkyHOHV5 X-Received: by 2002:a5d:4d4b:: with SMTP id a11-v6mr11805865wru.40.1538498161385; Tue, 02 Oct 2018 09:36:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538498161; cv=none; d=google.com; s=arc-20160816; b=oW/zNPnnHR/hb/Idg+9agSFP3/Dd6wGh5bvEFrO1tWCcwVj+5JS7eebZ2CDojvYt/k 2MNNplGsm6M9SbTT2K+veB8zfcY/CXeLRNdspU6mM4RYQhzQgAR/UDZEZlwXAb7Zn2XM mPM80CqC7RUYtp19gRGY0aW8E7Z1Eq6LLqkF43kuUy7o5XhK5gDMabNEbSjTUKdqcyjw w/y1bacTG/t2M7W19HDWD/3193nY5GFynfQx9MzY87kEjxGZRRuaoCAbJk49yMl7vlte QQtN46E7O/uGBuoNbGFRMO1kWjErCVB3K5FciVv73WwOjTuh+DOU17VC9AR8HUeRBsOU OUjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=T4S0xeLRiuwbo6rPdWtjgnSVqlnJWrAcCr7jy1IhKfs=; b=0W3sE0cNn7O643gMbT1QXOlAo1A40lyoIWO1iHqhy0PPe/0FSXckrrZQUr5oKPSK09 Re22ZIlWrxWO6lGEXEsG2dHJPQEyiXUDOoCht7Ty1Quc0kwQ1mYxd9fodMSKNQ+5Qdkb BijpgABeV3cxakhs7b2I6yUz2N/xD62YEZjRcd7c3tRc/5GhFyW+htFZDMzsWSN85anr eU+nd+a2kFuEnnQWRLhkFfFWnaVUCEN5SLtDfNJXkqlqBOsqkh2Q8hgFh8wipAVw3I/6 a2AgQFT27iirKAXazBXriO2x2kK+EGGiVClR109+f3bLskdv4hmuS122eKNaqN/rLRaA 41vg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id q12-v6si2370836wrw.84.2018.10.02.09.36.01 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 Oct 2018 09:36:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1g7NeS-0007Gj-TY; Tue, 02 Oct 2018 17:36:00 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 02/13] target/arm: Define new EXCP type for v8M stack overflows Date: Tue, 2 Oct 2018 17:35:45 +0100 Message-Id: <20181002163556.10279-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181002163556.10279-1-peter.maydell@linaro.org> References: <20181002163556.10279-1-peter.maydell@linaro.org> MIME-Version: 1.0 Define EXCP_STKOF, and arrange for it to cause us to take a UsageFault with CFSR.STKOF set. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 5 +++++ 2 files changed, 7 insertions(+) -- 2.19.0 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d2c1d005ed7..318792823b9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -56,6 +56,7 @@ #define EXCP_SEMIHOST 16 /* semihosting call */ #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ +#define EXCP_STKOF 19 /* v8M STKOF UsageFault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ #define ARMV7M_EXCP_RESET 1 @@ -1380,6 +1381,7 @@ FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) FIELD(V7M_CFSR, INVPC, 16 + 2, 1) FIELD(V7M_CFSR, NOCP, 16 + 3, 1) +FIELD(V7M_CFSR, STKOF, 16 + 4, 1) FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6ed8631dbee..c303dc453f1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7511,6 +7511,7 @@ static void arm_log_exception(int idx) [EXCP_SEMIHOST] = "Semihosting call", [EXCP_NOCP] = "v7M NOCP UsageFault", [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", + [EXCP_STKOF] = "v8M STKOF UsageFault", }; if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { @@ -7666,6 +7667,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; break; + case EXCP_STKOF: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; + break; case EXCP_SWI: /* The PC already points to the next instruction. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);