From patchwork Tue Oct 2 16:35:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148002 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5372174lji; Tue, 2 Oct 2018 09:36:05 -0700 (PDT) X-Google-Smtp-Source: ACcGV61AwWqf/IrfJLlXkhXbcu0bN4/xllLzCr6vi9M0stUyE0LRO92mQg/+mDeSbDiT9E1vPZ+/ X-Received: by 2002:adf:e681:: with SMTP id r1-v6mr11552371wrm.294.1538498165061; Tue, 02 Oct 2018 09:36:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538498165; cv=none; d=google.com; s=arc-20160816; b=g0oDU3Wf5MQWWTLGGrTlOJ3oIxrcWSa4CMUQanbIU6q8/dTBgiNbrkzxl5ghqVXB9t i0Oxpcw0F/SDUNhFA3LrmAMeGxajZ/LmrmY34HDTwngJ4uRoxv+hNTqaqRzAU7XixIv2 Rd3s6lmbCbnaN6LgoM50n54rLJPmXxSWWrRup1q2WpmBAOhwD6KV0jy2SR0vP0iG9eCi 5ldQ6isTuElFMiQ3ocN6qXNiML3+t/IRsq4WvWQGLy9dPHqEoWkjEykSqA4jH6LiRPsD Oj9z9IZxGGy7plAFSgHEXuoasLoOpWVzhj4TfKsVT1g7JqYL+cTup3k6KpGDkHW6wvCX cyKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=KCDU3/ohzWCYsOb4tRry/i55uImP2+JAdClztFl2B9w=; b=Y9pRzMrjAIKLXs8BMhx8SYdAUB+fmaogIzbtmikvznG3GMm3zeFJdne7jYvaRA62B3 sQhObJPHwkCHnuPlJRcqvnIIzli4ivCPkqYBjEWrXpEhSoX9hAiZK1mHmfseoN3XAEZi 3CpJd6ZvJvVMUgfDSwPYmPu5UEeIOFr64P7wxY5/+jYW3alW0cFrOfOVs4+AUtSLipYv NulPGFFxa63d7EkNmZ/aABA1jsezihKJcjW2Mj2iSCrTSWR6Ci2ZKXQakL7QauBTBSTk l696gzu2gJdzTxxDjs/p1OsRld32gE/2TiYzTGtEZvljPzfOVpHnjLakvx4oCqmVQSW0 Cqsw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 35-v6si14675158wra.136.2018.10.02.09.36.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 Oct 2018 09:36:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1g7NeW-0007Hc-JH; Tue, 02 Oct 2018 17:36:04 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 05/13] target/arm: Add some comments in Thumb decode Date: Tue, 2 Oct 2018 17:35:48 +0100 Message-Id: <20181002163556.10279-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181002163556.10279-1-peter.maydell@linaro.org> References: <20181002163556.10279-1-peter.maydell@linaro.org> MIME-Version: 1.0 Add some comments to the Thumb decoder indicating what bits of the instruction have been decoded at various points in the code. This is not an exhaustive set of comments; we're gradually adding comments as we work with particular bits of the code. Signed-off-by: Peter Maydell --- Specifically, I figured these out as I was going through looking for the insns which write SP. These comments turn out not to be relevant to those instructions, but I don't want to throw them away. --- target/arm/translate.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) -- 2.19.0 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/target/arm/translate.c b/target/arm/translate.c index 25a8fe672f5..fcb33b8a503 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10623,6 +10623,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp2 = load_reg(s, rm); if ((insn & 0x70) != 0) goto illegal_op; + /* + * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx: + * - MOV, MOVS (register-shifted register), flagsetting + */ op = (insn >> 21) & 3; logic_cc = (insn & (1 << 20)) != 0; gen_arm_shift_reg(tmp, op, tmp2, logic_cc); @@ -11674,7 +11678,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) rd = insn & 7; op = (insn >> 11) & 3; if (op == 3) { - /* add/subtract */ + /* + * 0b0001_1xxx_xxxx_xxxx + * - Add, subtract (three low registers) + * - Add, subtract (two low registers and immediate) + */ rn = (insn >> 3) & 7; tmp = load_reg(s, rn); if (insn & (1 << 10)) { @@ -11711,7 +11719,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; case 2: case 3: - /* arithmetic large immediate */ + /* + * 0b001x_xxxx_xxxx_xxxx + * - Add, subtract, compare, move (one low register and immediate) + */ op = (insn >> 11) & 3; rd = (insn >> 8) & 0x7; if (op == 0) { /* mov */ @@ -11848,7 +11859,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } - /* data processing register */ + /* + * 0b0100_00xx_xxxx_xxxx + * - Data-processing (two low registers) + */ rd = insn & 7; rm = (insn >> 3) & 7; op = (insn >> 6) & 0xf;