From patchwork Tue Oct 16 09:37:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148927 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4849018lji; Tue, 16 Oct 2018 02:37:08 -0700 (PDT) X-Google-Smtp-Source: ACcGV63/aDfQWbKbj9WyFHGRqWtVNQGzfocG7KXVNToOJQ+wcbiNj+HT7BxGR2i+iJ9vjd+lIr+5 X-Received: by 2002:a2e:50e:: with SMTP id 14-v6mr13091465ljf.152.1539682628670; Tue, 16 Oct 2018 02:37:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539682628; cv=none; d=google.com; s=arc-20160816; b=Mhv+oTO57kcEEcj1LzQdGg6giI557sUoJCyjDbMuy4z8y1TNZdd5RMwELSbRyMphOh rAszjDO8mUDJ0TJI6Wf1cbkVpAc99XyCr4XEq4nKmErgzeSMWmYsYWNGIAvMXnb46GyG ksHBg3TAzXlJ/2qx9udmK5m96a/4CWa6Y0MPq+0YnRMgqi8hBzelWeNvoKkVCNx/VHyF JMMC8TK9wlBPhvXMN8BlNYAxzJaUfhdQBmcjxr54UBhI5XL9FlXWwO0YQXhTFsmABq3r AV9ipV7+hvshq3V4ei2a2NvZsWzS3ZOac6+1izyi67TZ5w0gn5BdsmTWj81+q8ilJr0h yIMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=ckMmZOuh7mIM28RxoB/ADTNpJIvKIT2+iOTSzCjfZ74=; b=1CO94ljYQ0U4O7SpEWm7rj5zlk5kOWlVWPkAaUScCYHUgRQxGx7pCeH4QWpGk653Dp kxITAoSgVB5FSoS2rO22HWrqQYkmiPkvoojUKqRFF+4gC/3cT/RM99D7jKMAAVrRm5yG Kcl/R0lJ9bwUFRRmiZTqVdvlb4WVQy/1TH81iwPm5UwPMJZbWQjG4D0AZT91I0Vkm0gV oAS/dz+To2/eEcQDPHc/Io8P68O37VHrCa990wXzmSGjkhT0snq3h3/P5PuN8SiaJFpt GweYWnatgLjl/yYRQ4P8A+i9rS4ULgTCR9BUuCKZc4U6agfxS2VLEFXYqSGygV+qfGeC OJDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id w5-v6si12572598ljj.69.2018.10.16.02.37.08 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 02:37:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCLml-0003Xq-Ld; Tue, 16 Oct 2018 10:37:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 1/2] target/arm: Set S and PTW in 64-bit PAR format Date: Tue, 16 Oct 2018 10:37:02 +0100 Message-Id: <20181016093703.10637-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016093703.10637-1-peter.maydell@linaro.org> References: <20181016093703.10637-1-peter.maydell@linaro.org> MIME-Version: 1.0 In do_ats_write() we construct a PAR value based on the result of the translation. A comment says "S2WLK and FSTAGE are always zero, because we don't implement virtualization". Since we do in fact now implement virtualization, add the missing code that sets these bits based on the reported ARMMMUFaultInfo. (These bits are named PTW and S in ARMv8, so we follow that convention in the new comments in this patch.) Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.19.0 Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index 43afdd082e1..dc849b09893 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2344,10 +2344,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= 1; /* F */ par64 |= (fsr & 0x3f) << 1; /* FS */ - /* Note that S2WLK and FSTAGE are always zero, because we don't - * implement virtualization and therefore there can't be a stage 2 - * fault. - */ + if (fi.stage2) { + par64 |= (1 << 9); /* S */ + } + if (fi.s1ptw) { + par64 |= (1 << 8); /* PTW */ + } } } else { /* fsr is a DFSR/IFSR value for the short descriptor