From patchwork Fri Oct 19 16:56:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 149327 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3587105lji; Fri, 19 Oct 2018 10:36:34 -0700 (PDT) X-Google-Smtp-Source: ACcGV62U4wK/hDScCXAg+a0shvqnBGumgbOzrqUvlgX0LAki+ZMHCMXn9VWh2L4pFFGZtle/g3jh X-Received: by 2002:a37:cfc7:: with SMTP id v68-v6mr33539698qkl.35.1539970594310; Fri, 19 Oct 2018 10:36:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539970594; cv=none; d=google.com; s=arc-20160816; b=Xx0IoJwlMn81NG3t5maX1P1G5zhc+uaMSaXP1KM2Zf40xbmNaBtXFqhMkxEmET+fyx LmR7GVQR1BhJVyEaBVCAb600pI38GESHhIL5teDL1oDi/IDFpBEfv62xWGSNNtwMq6kf VpdZGwQm4FZVsWVdpKeCS/h9g6/xLz2uXKk29fRvmDYVlBwgYTfL/Ce9raQ/+91H0CEo wd/OEfDwyDozP/klyAa0Bwnp5INddpomoEcEl3yDpczQQjk/Tl0EP2aIvHacGYvEDsEE OB7csCKzE8kh6w7cEJAIB1WdrmKznlgmqrY1M05HZT2anz/WgRtlW3RirtifBDo7+9Ji 3bow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=EWJAg6ABCuBm7erbGxiG/HhvHLNA/MCiGJvHyOMhwxo=; b=qERlv2HRSrbO8bQ6d3K9Bye0j0+DwI9lpZAkZLWXxuRoWDh5qM2VtoqPEWTOmweoel 285LFdsOXb9k0hxNJZixW8K25xNNhSzWioCt4hHcNra7O4AB5q4j6aOwYtdVOd+cowtp itmsxG9fzTMH2/DNeh/upPPhfnqxD4dwOxdnO9TvyZhzubWhSiyshmPrbDoZtqfUtadr /ITKbcNcTNTOhAE5FgRW/cQDuECRtXTkS+ZEx8zLq8/bfH8mFbX7SOuSJRFbxMmgbvsq 8mG/O8u1Y/cuhaRO2lcwdHLS8vmLy7OFBGjrsqvMVUyNcsm+laIwMobENb+8tmkRQ9cX reXg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id t7si8566704qvt.132.2018.10.19.10.36.34 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 19 Oct 2018 10:36:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51920 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDYhN-0006Gu-Nx for patch@linaro.org; Fri, 19 Oct 2018 13:36:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDY5q-0001Or-B7 for qemu-devel@nongnu.org; Fri, 19 Oct 2018 12:57:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDY5p-0001uv-1q for qemu-devel@nongnu.org; Fri, 19 Oct 2018 12:57:46 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51974) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDY5o-0001qj-Ow for qemu-devel@nongnu.org; Fri, 19 Oct 2018 12:57:44 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gDY5n-0006gc-EU for qemu-devel@nongnu.org; Fri, 19 Oct 2018 17:57:43 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 19 Oct 2018 17:56:56 +0100 Message-Id: <20181019165735.22511-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181019165735.22511-1-peter.maydell@linaro.org> References: <20181019165735.22511-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/45] target/arm: Convert division from feature bits to isar0 tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Both arm and thumb2 division are controlled by the same ISAR field, which takes care of the arm implies thumb case. Having M imply thumb2 division was wrong for cortex-m0, which is v6m and does not have thumb2 at all, much less thumb2 division. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-id: 20181016223115.24100-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++-- linux-user/elfload.c | 4 ++-- target/arm/cpu.c | 10 +--------- target/arm/translate.c | 4 ++-- 4 files changed, 15 insertions(+), 15 deletions(-) -- 2.19.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1c0712fe840..f1c2ec64616 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1563,7 +1563,6 @@ enum arm_features { ARM_FEATURE_VFP3, ARM_FEATURE_VFP_FP16, ARM_FEATURE_NEON, - ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ ARM_FEATURE_THUMB2EE, @@ -1573,7 +1572,6 @@ enum arm_features { ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ - ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ ARM_FEATURE_GENERIC_TIMER, ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ @@ -3152,6 +3150,16 @@ extern const uint64_t pred_esz_masks[4]; /* * 32-bit feature tests via id registers. */ +static inline bool isar_feature_thumb_div(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; +} + +static inline bool isar_feature_arm_div(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 97014959ff3..1e0f22d812b 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -471,8 +471,8 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); - GET_FEATURE(ARM_FEATURE_ARM_DIV, ARM_HWCAP_ARM_IDIVA); - GET_FEATURE(ARM_FEATURE_THUMB_DIV, ARM_HWCAP_ARM_IDIVT); + GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); + GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c. * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6f27c33b555..9319f92f1f3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -829,7 +829,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - set_feature(env, ARM_FEATURE_ARM_DIV); + assert(cpu_isar_feature(arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -862,12 +862,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); } - if (arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_THUMB_DIV); - } - if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { - set_feature(env, ARM_FEATURE_THUMB_DIV); - } if (arm_feature(env, ARM_FEATURE_VFP4)) { set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_VFP_FP16); @@ -1388,8 +1382,6 @@ static void cortex_r5_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); - set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_PMSA); cpu->midr = 0x411fc153; /* r1p3 */ diff --git a/target/arm/translate.c b/target/arm/translate.c index f6215951970..8b2be714390 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9755,7 +9755,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 1: case 3: /* SDIV, UDIV */ - if (!arm_dc_feature(s, ARM_FEATURE_ARM_DIV)) { + if (!dc_isar_feature(arm_div, s)) { goto illegal_op; } if (((insn >> 5) & 7) || (rd != 15)) { @@ -10963,7 +10963,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp2 = load_reg(s, rm); if ((op & 0x50) == 0x10) { /* sdiv, udiv */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DIV)) { + if (!dc_isar_feature(thumb_div, s)) { goto illegal_op; } if (op & 0x20)