From patchwork Mon Oct 29 15:53:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149686 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4359953ljp; Mon, 29 Oct 2018 09:33:41 -0700 (PDT) X-Google-Smtp-Source: AJdET5fqUmmqGglWXxS3nFlFY3EJ6mfx6EX0wLC/hVPPZNLe/kQPLKJnO1cYWWrVJk8oIG5KM2Cl X-Received: by 2002:a0c:f0c2:: with SMTP id d2mr1583536qvl.123.1540830821033; Mon, 29 Oct 2018 09:33:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540830821; cv=none; d=google.com; s=arc-20160816; b=mO87doyfQqQF6JGoRvvXACAjXuJB+v5Wrj6Hnuq5VHXEpgZJCDeEKCHv6uujgwhQfy g8on04+tT6tNn2MuTLX6roux6c+VOW0abRfytQah4l7qI4Kk/fO6x/vjg4P1oWUQf3+F glP7KTvCqmtfKtw50tp4NmrLhqyMZV/EFb8v0GTerGCFJM1LBFTB6kL0ZL3H6vAQVUzY MBvgYuEQjdUT0a0eFHaWJ0gp4g0ZD3pCeyX64FSW00wIFv+MJckV4XUzb/mKePStKVDz 5zZOqdSu+1tmAkz/q5/DMYqsINfOgvgacDCHy3sUBUNkeESiOILWrHUzFWzIx7/SUHYO /AZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ufjQzo+SI6PyAb64orKIBD88Q1YJp7NUSWPWGJqPOn4=; b=sf4vJE95KWS0Ra7TNXprJS2NCXXnIgdKfygtg6hX+J0pRq4AU1pnQ/MuSKcc5Ee+rn jVQCrR/mOCh0QhZyU0kwFHyDfjIQP9tCIBG1MjrCI5MCzaGGW9Vxu3shVgS4o9NHW/Uk I8w7hLp59PLGlSCpoA2NJ4wGOuVk3gazBqG4ittN4oy4JIUYgi3+UvwKSeUbH0YT8phd NHkVNT983US7aHrxXW6K/MB2bOCsNZmdrs/+XUyZd2n5c7awJUy42eG6k2CfleFm0TGr o1rrw775ilSn7xDw0uIAYDigWcMUcqyrrxNEkzAUEE0hhD7ChmdHWiyHfYHfK9osDM+K M22w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Oo+yuyFv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id x124-v6si4663446qka.84.2018.10.29.09.33.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 29 Oct 2018 09:33:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Oo+yuyFv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46743 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHAU0-0007C5-Cd for patch@linaro.org; Mon, 29 Oct 2018 12:33:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47173) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9rk-0000gI-TM for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9re-0000in-Gv for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:05 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:33163) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gH9rX-0000Xh-Cx for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:57 -0400 Received: by mail-wr1-x443.google.com with SMTP id u1-v6so9295862wrn.0 for ; Mon, 29 Oct 2018 08:53:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ufjQzo+SI6PyAb64orKIBD88Q1YJp7NUSWPWGJqPOn4=; b=Oo+yuyFvZwr7PLQVKIFhdYqNIUdgiB1UnEkCk2Cxjp7fKepzW4i/2RLYyOy+vWYmIS Z/pPgeNPPVdEg2K8d56y6aqRlVzh27xRq5Co/epQeq+lCMHX/BTwUiJlIcNz3+XMxGdR 3sevnYGfDe6Bwhf+7YbFGNIykiv4wSmUBKLLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ufjQzo+SI6PyAb64orKIBD88Q1YJp7NUSWPWGJqPOn4=; b=Cu2Z9hdssmQ7kMF5J4NgLh7xjuqG+7wD0AXf+RhqdaY9AxnoANiA6FdtPqX+OPgYeA R5aJm3S1rCOMLYKpZdggPXnR+Ze9moI1aORdbSX1TDU9BM4rMSPbXPeAw7Evv/+mkKF4 VACO4gp7QhcMPYrzp2vbcZt+65gd5OJKWlA6ucw+zqkC8JnNpvch6isgWGr9uEOaWerJ 4RS6yuP9cTiB6Vg2J40ioDk+hd3Bpyp9WGYoILqZnhvCTA1I5Lq8JRSfiBdtsDevnUlD F18d7cVWM2P5FFwy9I4+FxpCBIhm+VHRVCr8XwD/5wXZeY8Q65ao0ToqoPqje9JymSdX o2Ww== X-Gm-Message-State: AGRZ1gITt1Xsr1tdLkKc8ScCuT2YlMInbxDMxbANUwyrj89uKDa5EHG+ KV2j/RWyoiGCvXIZqPtLiFupt2csUcQ= X-Received: by 2002:adf:ca03:: with SMTP id o3-v6mr4998017wrh.148.1540828428616; Mon, 29 Oct 2018 08:53:48 -0700 (PDT) Received: from cloudburst.twiddle.net ([5.148.65.242]) by smtp.gmail.com with ESMTPSA id p3-v6sm4700517wre.47.2018.10.29.08.53.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Oct 2018 08:53:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 15:53:38 +0000 Message-Id: <20181029155339.15280-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181029155339.15280-1-richard.henderson@linaro.org> References: <20181029155339.15280-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Install ASIDs for short-form from EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is less complex than the LPAE case, but still we now avoid the flush in case it is only the PROCID field that is changing. Signed-off-by: Richard Henderson --- target/arm/helper.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 26d6f28793..f767467dcf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -541,17 +541,31 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); - - if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) - && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table - * format) this register includes the ASID, so do a TLB flush. - * For PMSA it is purely a process ID and no action is needed. - */ - tlb_flush(CPU(cpu)); - } raw_write(env, ri, value); + + /* + * For VMSA (when not using the LPAE long descriptor page table format) + * this register includes the ASID. For PMSA it is purely a process ID + * and no action is needed. + */ + if (!arm_feature(env, ARM_FEATURE_PMSA) && + !extended_addresses_enabled(env)) { + CPUState *cs = CPU(arm_env_get_cpu(env)); + int asid = extract32(value, 0, 8); + int idxmask; + + switch (ri->secure) { + case ARM_CP_SECSTATE_S: + idxmask = ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + break; + case ARM_CP_SECSTATE_NS: + idxmask = ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + break; + default: + g_assert_not_reached(); + } + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); + } } /* IS variants of TLB operations must affect all cores */