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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 6-v6si32244423ybq.288.2018.11.23.07.20.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:20:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XDdC8TkT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52967 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQDG4-000857-2B for patch@linaro.org; Fri, 23 Nov 2018 10:20:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj9-0000LP-CM for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj7-0003qN-F9 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:38435) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj7-0003pL-9N for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:37 -0500 Received: by mail-wr1-x444.google.com with SMTP id v13so9118649wrw.5 for ; Fri, 23 Nov 2018 06:46:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b79TMT1xsQ1kNxl+TOgvq76GlDxOHE/SHes3qAZINQQ=; b=XDdC8TkT/H6QSB8JQTTABNVFnIRdHU/W7JMCrNR4qkXUMIa8UpH3PsijCoG1S5idE+ /0Tf9y8QVrTvp7Kvfgr15KZBZm9RM05aoCln5X+Cbvlnt1RKh4WgWfNzHYkq4pJTTTBx RnRH9R2fcOziWeWBWtwJhBObgDr0uRjBQykyI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b79TMT1xsQ1kNxl+TOgvq76GlDxOHE/SHes3qAZINQQ=; b=ATmlztqKhW6ZLUWBjTN0CLoNfB6nZfAL9h/bDQVDaUCZ0wS+9zlht3N4ehrG4z4Hmk 8+BALXe6TxLXd1p8DjJ/wD4DOKIG+D9NNhRzGhR6+PUlrIzZigzp/jV3GUgtMdRpJ7hY Lyv0rpA8aBO1jFYb96R/Q66YMuumdSIv6GoxqMm5PtniFnwuJ/iZpgFnp5OIYJTz0p4a hvARk1JK2c5dNsur1+OLci5CoEBKd5qhuoEeQiMTFmzAoTVdh1tClUffBEdcdje2A9eU qX07+qeP9Vr7PEYbDb+c7jQEzT5A+zMWP/GhkK7hjQ7lRvL5+DphCn+lra6x0VyC/K+R 7w9Q== X-Gm-Message-State: AA+aEWaRMAwVWnb0rm1BwRZjk7TmCcnrQndQ8g/Tp6q5XvpO/H/ONtg6 lJ3p4K7iYA82QucrvbwvxiIHAWWEwD2v8A== X-Received: by 2002:a5d:46c2:: with SMTP id g2mr14796626wrs.49.1542984396072; Fri, 23 Nov 2018 06:46:36 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:58 +0100 Message-Id: <20181123144558.5048-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 37/37] tcg/i386: Remove L constraint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We no longer need any scratch registers for user-only memory ops. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 19a0fa8a03..2815dd25a0 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -240,10 +240,7 @@ static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) #else static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) { - if (TCG_TARGET_REG_BITS == 64) { - /* Temps are still needed for guest_base && !guest_base_flags. */ - return "L"; - } else if (type == ARG_STVAL && !is_64) { + if (TCG_TARGET_REG_BITS == 32 && type == ARG_STVAL && !is_64) { /* Byte stores must happen from q-regs. Because of this, we must * constrain all INDEX_op_qemu_st_i32 to use q-regs. */ @@ -353,14 +350,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->u.regs |= ALL_VECTOR_REGS; break; - /* qemu_ld/st address constraint */ - case 'L': - ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); - break; - case 'e': ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32); break;