| Message ID | 20181203203839.757-3-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: LOR, HPD, AA32HPD | expand |
On Mon, 3 Dec 2018 at 20:38, Richard Henderson <richard.henderson@linaro.org> wrote: > > Post v8.3 bits taken from SysReg_v85_xml-00bet8. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 22 +++++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 656a96a8f8..79d58978f7 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1249,7 +1249,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) > #define HCR_TIDCP (1ULL << 20) > #define HCR_TACR (1ULL << 21) > #define HCR_TSW (1ULL << 22) > -#define HCR_TPC (1ULL << 23) > +#define HCR_TPCP (1ULL << 23) We were using "TPC" here because that's what the 32-bit HCR register names the bit; but standardizing on the 64-bit HCR_EL2 names makes sense. thanks -- PMM
On Thu, 6 Dec 2018 at 11:15, Peter Maydell <peter.maydell@linaro.org> wrote: > > On Mon, 3 Dec 2018 at 20:38, Richard Henderson > <richard.henderson@linaro.org> wrote: > > > > Post v8.3 bits taken from SysReg_v85_xml-00bet8. > > > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > > --- > > target/arm/cpu.h | 22 +++++++++++++++++++++- > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > index 656a96a8f8..79d58978f7 100644 > > --- a/target/arm/cpu.h > > +++ b/target/arm/cpu.h > > @@ -1249,7 +1249,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) > > #define HCR_TIDCP (1ULL << 20) > > #define HCR_TACR (1ULL << 21) > > #define HCR_TSW (1ULL << 22) > > -#define HCR_TPC (1ULL << 23) > > +#define HCR_TPCP (1ULL << 23) > > We were using "TPC" here because that's what the 32-bit HCR > register names the bit; but standardizing on the 64-bit HCR_EL2 > names makes sense. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 656a96a8f8..79d58978f7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1249,7 +1249,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_TIDCP (1ULL << 20) #define HCR_TACR (1ULL << 21) #define HCR_TSW (1ULL << 22) -#define HCR_TPC (1ULL << 23) +#define HCR_TPCP (1ULL << 23) #define HCR_TPU (1ULL << 24) #define HCR_TTLB (1ULL << 25) #define HCR_TVM (1ULL << 26) @@ -1261,6 +1261,26 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_CD (1ULL << 32) #define HCR_ID (1ULL << 33) #define HCR_E2H (1ULL << 34) +#define HCR_TLOR (1ULL << 35) +#define HCR_TERR (1ULL << 36) +#define HCR_TEA (1ULL << 37) +#define HCR_MIOCNCE (1ULL << 38) +#define HCR_APK (1ULL << 40) +#define HCR_API (1ULL << 41) +#define HCR_NV (1ULL << 42) +#define HCR_NV1 (1ULL << 43) +#define HCR_AT (1ULL << 44) +#define HCR_NV2 (1ULL << 45) +#define HCR_FWB (1ULL << 46) +#define HCR_FIEN (1ULL << 47) +#define HCR_TID4 (1ULL << 49) +#define HCR_TICAB (1ULL << 50) +#define HCR_TOCU (1ULL << 52) +#define HCR_TTLBIS (1ULL << 54) +#define HCR_TTLBOS (1ULL << 55) +#define HCR_ATA (1ULL << 56) +#define HCR_DCT (1ULL << 57) + /* * When we actually implement ARMv8.1-VHE we should add HCR_E2H to * HCR_MASK and then clear it again if the feature bit is not set in
Post v8.3 bits taken from SysReg_v85_xml-00bet8. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) -- 2.17.2