diff mbox series

[17/34] target/ppc: convert VMX logical instructions to use vector operations

Message ID 20181218063911.2112-18-richard.henderson@linaro.org
State New
Headers show
Series tcg, target/ppc vector improvements | expand

Commit Message

Richard Henderson Dec. 18, 2018, 6:38 a.m. UTC
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20181217122405.18732-9-mark.cave-ayland@ilande.co.uk>
---
 target/ppc/translate.c              |  1 +
 target/ppc/translate/vmx-impl.inc.c | 63 ++++++++++++++++-------------
 2 files changed, 37 insertions(+), 27 deletions(-)

-- 
2.17.2

Comments

David Gibson Dec. 19, 2018, 6:29 a.m. UTC | #1
On Mon, Dec 17, 2018 at 10:38:54PM -0800, Richard Henderson wrote:
> From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

> 

> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


Acked-by: David Gibson <david@gibson.dropbear.id.au>


> Message-Id: <20181217122405.18732-9-mark.cave-ayland@ilande.co.uk>

> ---

>  target/ppc/translate.c              |  1 +

>  target/ppc/translate/vmx-impl.inc.c | 63 ++++++++++++++++-------------

>  2 files changed, 37 insertions(+), 27 deletions(-)

> 

> diff --git a/target/ppc/translate.c b/target/ppc/translate.c

> index 8e89aec14d..1b61bfa093 100644

> --- a/target/ppc/translate.c

> +++ b/target/ppc/translate.c

> @@ -24,6 +24,7 @@

>  #include "disas/disas.h"

>  #include "exec/exec-all.h"

>  #include "tcg-op.h"

> +#include "tcg-op-gvec.h"

>  #include "qemu/host-utils.h"

>  #include "exec/cpu_ldst.h"

>  

> diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c

> index 75d2b2280f..c13828a09d 100644

> --- a/target/ppc/translate/vmx-impl.inc.c

> +++ b/target/ppc/translate/vmx-impl.inc.c

> @@ -262,41 +262,50 @@ GEN_VX_VMUL10(vmul10euq, 1, 0);

>  GEN_VX_VMUL10(vmul10cuq, 0, 1);

>  GEN_VX_VMUL10(vmul10ecuq, 1, 1);

>  

> -/* Logical operations */

> -#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3)                        \

> -static void glue(gen_, name)(DisasContext *ctx)                                 \

> +#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3)                    \

> +static void glue(gen_, name)(DisasContext *ctx)                         \

>  {                                                                       \

> -    TCGv_i64 t0 = tcg_temp_new_i64();                                   \

> -    TCGv_i64 t1 = tcg_temp_new_i64();                                   \

> -    TCGv_i64 avr = tcg_temp_new_i64();                                  \

> -                                                                        \

>      if (unlikely(!ctx->altivec_enabled)) {                              \

>          gen_exception(ctx, POWERPC_EXCP_VPU);                           \

>          return;                                                         \

>      }                                                                   \

> -    get_avr64(t0, rA(ctx->opcode), true);                               \

> -    get_avr64(t1, rB(ctx->opcode), true);                               \

> -    tcg_op(avr, t0, t1);                                                \

> -    set_avr64(rD(ctx->opcode), avr, true);                              \

>                                                                          \

> -    get_avr64(t0, rA(ctx->opcode), false);                              \

> -    get_avr64(t1, rB(ctx->opcode), false);                              \

> -    tcg_op(avr, t0, t1);                                                \

> -    set_avr64(rD(ctx->opcode), avr, false);                             \

> -                                                                        \

> -    tcg_temp_free_i64(t0);                                              \

> -    tcg_temp_free_i64(t1);                                              \

> -    tcg_temp_free_i64(avr);                                             \

> +    tcg_op(vece,                                                        \

> +           avr64_offset(rD(ctx->opcode), true),                         \

> +           avr64_offset(rA(ctx->opcode), true),                         \

> +           avr64_offset(rB(ctx->opcode), true),                         \

> +           16, 16);                                                     \

>  }

>  

> -GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);

> -GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);

> -GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);

> -GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);

> -GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);

> -GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);

> -GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);

> -GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);

> +#define GEN_VXFORM_VN(name, vece, tcg_op, opc2, opc3)                   \

> +static void glue(gen_, name)(DisasContext *ctx)                         \

> +{                                                                       \

> +    if (unlikely(!ctx->altivec_enabled)) {                              \

> +        gen_exception(ctx, POWERPC_EXCP_VPU);                           \

> +        return;                                                         \

> +    }                                                                   \

> +                                                                        \

> +    tcg_op(vece,                                                        \

> +           avr64_offset(rD(ctx->opcode), true),                         \

> +           avr64_offset(rA(ctx->opcode), true),                         \

> +           avr64_offset(rB(ctx->opcode), true),                         \

> +           16, 16);                                                     \

> +                                                                        \

> +    tcg_gen_gvec_not(vece,                                              \

> +                     avr64_offset(rD(ctx->opcode), true),               \

> +                     avr64_offset(rD(ctx->opcode), true),               \

> +                     16, 16);                                           \

> +}

> +

> +/* Logical operations */

> +GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);

> +GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);

> +GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);

> +GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);

> +GEN_VXFORM_VN(vnor, MO_64, tcg_gen_gvec_or, 2, 20);

> +GEN_VXFORM_VN(veqv, MO_64, tcg_gen_gvec_xor, 2, 26);

> +GEN_VXFORM_VN(vnand, MO_64, tcg_gen_gvec_and, 2, 22);

> +GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);

>  

>  #define GEN_VXFORM(name, opc2, opc3)                                    \

>  static void glue(gen_, name)(DisasContext *ctx)                                 \


-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
diff mbox series

Patch

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 8e89aec14d..1b61bfa093 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -24,6 +24,7 @@ 
 #include "disas/disas.h"
 #include "exec/exec-all.h"
 #include "tcg-op.h"
+#include "tcg-op-gvec.h"
 #include "qemu/host-utils.h"
 #include "exec/cpu_ldst.h"
 
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 75d2b2280f..c13828a09d 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -262,41 +262,50 @@  GEN_VX_VMUL10(vmul10euq, 1, 0);
 GEN_VX_VMUL10(vmul10cuq, 0, 1);
 GEN_VX_VMUL10(vmul10ecuq, 1, 1);
 
-/* Logical operations */
-#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3)                        \
-static void glue(gen_, name)(DisasContext *ctx)                                 \
+#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3)                    \
+static void glue(gen_, name)(DisasContext *ctx)                         \
 {                                                                       \
-    TCGv_i64 t0 = tcg_temp_new_i64();                                   \
-    TCGv_i64 t1 = tcg_temp_new_i64();                                   \
-    TCGv_i64 avr = tcg_temp_new_i64();                                  \
-                                                                        \
     if (unlikely(!ctx->altivec_enabled)) {                              \
         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
         return;                                                         \
     }                                                                   \
-    get_avr64(t0, rA(ctx->opcode), true);                               \
-    get_avr64(t1, rB(ctx->opcode), true);                               \
-    tcg_op(avr, t0, t1);                                                \
-    set_avr64(rD(ctx->opcode), avr, true);                              \
                                                                         \
-    get_avr64(t0, rA(ctx->opcode), false);                              \
-    get_avr64(t1, rB(ctx->opcode), false);                              \
-    tcg_op(avr, t0, t1);                                                \
-    set_avr64(rD(ctx->opcode), avr, false);                             \
-                                                                        \
-    tcg_temp_free_i64(t0);                                              \
-    tcg_temp_free_i64(t1);                                              \
-    tcg_temp_free_i64(avr);                                             \
+    tcg_op(vece,                                                        \
+           avr64_offset(rD(ctx->opcode), true),                         \
+           avr64_offset(rA(ctx->opcode), true),                         \
+           avr64_offset(rB(ctx->opcode), true),                         \
+           16, 16);                                                     \
 }
 
-GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
-GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
-GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
-GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
-GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
-GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
-GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
-GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
+#define GEN_VXFORM_VN(name, vece, tcg_op, opc2, opc3)                   \
+static void glue(gen_, name)(DisasContext *ctx)                         \
+{                                                                       \
+    if (unlikely(!ctx->altivec_enabled)) {                              \
+        gen_exception(ctx, POWERPC_EXCP_VPU);                           \
+        return;                                                         \
+    }                                                                   \
+                                                                        \
+    tcg_op(vece,                                                        \
+           avr64_offset(rD(ctx->opcode), true),                         \
+           avr64_offset(rA(ctx->opcode), true),                         \
+           avr64_offset(rB(ctx->opcode), true),                         \
+           16, 16);                                                     \
+                                                                        \
+    tcg_gen_gvec_not(vece,                                              \
+                     avr64_offset(rD(ctx->opcode), true),               \
+                     avr64_offset(rD(ctx->opcode), true),               \
+                     16, 16);                                           \
+}
+
+/* Logical operations */
+GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
+GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
+GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
+GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
+GEN_VXFORM_VN(vnor, MO_64, tcg_gen_gvec_or, 2, 20);
+GEN_VXFORM_VN(veqv, MO_64, tcg_gen_gvec_xor, 2, 26);
+GEN_VXFORM_VN(vnand, MO_64, tcg_gen_gvec_and, 2, 22);
+GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
 
 #define GEN_VXFORM(name, opc2, opc3)                                    \
 static void glue(gen_, name)(DisasContext *ctx)                                 \