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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:09 -0800 Message-Id: <20181218063911.2112-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change the representation of VSCR_SAT such that it is easy to set from vector code. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 +++- target/ppc/int_helper.c | 11 ++++++++--- 2 files changed, 11 insertions(+), 4 deletions(-) -- 2.17.2 Acked-by: David Gibson diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a2fe6058b1..26d2e16720 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1063,10 +1063,12 @@ struct CPUPPCState { /* Special purpose registers */ target_ulong spr[1024]; ppc_spr_t spr_cb[1024]; - /* Vector status and control register */ + /* Vector status and control register, minus VSCR_SAT. */ uint32_t vscr; /* VSX registers (including FP and AVR) */ ppc_vsr_t vsr[64] QEMU_ALIGNED(16); + /* Non-zero if and only if VSCR_SAT should be set. */ + ppc_vsr_t vscr_sat; /* SPE registers */ uint64_t spe_acc; uint32_t spe_fscr; diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 38aa3e85a6..9dbcbcd87a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -471,18 +471,23 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh) void helper_mtvscr(CPUPPCState *env, uint32_t vscr) { - env->vscr = vscr; + env->vscr = vscr & ~(1u << VSCR_SAT); + /* Which bit we set is completely arbitrary, but clear the rest. */ + env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT); + env->vscr_sat.u64[1] = 0; set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); } uint32_t helper_mfvscr(CPUPPCState *env) { - return env->vscr; + uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0; + return env->vscr | (sat << VSCR_SAT); } static inline void set_vscr_sat(CPUPPCState *env) { - env->vscr |= 1 << VSCR_SAT; + /* The choice of non-zero value is arbitrary. */ + env->vscr_sat.u32[0] = 1; } void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)