From patchwork Tue Jan 8 16:30:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154990 Delivered-To: patches@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5070129jaa; Tue, 8 Jan 2019 08:30:14 -0800 (PST) X-Received: by 2002:a5d:628a:: with SMTP id k10mr1896295wru.254.1546965014680; Tue, 08 Jan 2019 08:30:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546965014; cv=none; d=google.com; s=arc-20160816; b=0hxHHlcmOJgADLbyj+uCPz197v76Evx1Gw8MEKzQGLGWkzflKHvzngzBHXu5XBkxlQ nQ2pDVBEcRx1LebQ9sMOZXfTG5cilecCzkCwBW5YqPWIgPpfVXGyVp26JNR8gSikz+eP Rfa45ZeNxz3xQewIslTmG/ptJ3DBkXU0y7ztM71Ew90ZUeOKSJp/4HnFZ8+6TTxr4gq7 X8uurVrz9qOv1CgUuHUYv1gPbhvt2bIqDpO8gVSms9z3fJq5dcnLLxbneSegxqLiUHzV T6dO/1P6XvSnm27qwtMp6KLHPhga4XPDOhXRi7exxa39Y2LUJDeMfdkAXvZQaPnjfugi PqhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=YbQA+DVaTaDYVaQxTwMAtKAWfFrdJhgpXzSxOuBbRnM=; b=w/S/E8xHt1N3sM7g4xBJgFIWIk8D0v0NZwlUXQo6fE43pV7/YDXIBORmTN5a0ZT9W+ RSO9Zfs8WLSqnna24n1AOA7uWI+y/ZgLe/WvvpJrV2VnLI1qYs23vPYQ6/0aCqb+87yV 6AVzDkGM8zubEEtdpv5S88l0H4x42TmzlFLfPUBSy401y22OH4hZpk0HJku7SuHnqegj kQ3ckEcGBUb1xGT97Q2COnLbe/dOb44xverSsNh/HfAI4bE5iq2931lu2KrP+5lSqPT/ 8OXA/4lZuvSMpQ2088aCRBEABA6ePY43ZJlqJLFq+EL9U4SKtBuE8s+IS4QF67v6z94z RX0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GC4QfhBe; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id f193sor7486561wme.9.2019.01.08.08.30.14 for (Google Transport Security); Tue, 08 Jan 2019 08:30:14 -0800 (PST) Received-SPF: pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GC4QfhBe; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YbQA+DVaTaDYVaQxTwMAtKAWfFrdJhgpXzSxOuBbRnM=; b=GC4QfhBeddbU6aUBlbRYZ6v4jU+85Qu2Z5QAfue52hBcgixrikT7jYJEkJ5+VZZQvW QvvA/jW7wOjhKOfoGFVWD766/SlAYy0SsplNHAvRp5nfv2SBQ78DQrfGyjiaQzgPnV/j MwwW0MfxWHQqlqqCUIpcNgxUquHfZt4HUD4Tg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YbQA+DVaTaDYVaQxTwMAtKAWfFrdJhgpXzSxOuBbRnM=; b=qu9rHCmvEW+780qTpkAwXG6So6nQm6Lj+mS69AijGfCX0NBlu0CbKYV6F/yfKctAcQ rBwiq3TXnHe7fKcH42rRmZElUikNamQHh2wvsfykqpmiCbaU4slNCAev4mMiZiT8IrHU mF0tZ6+We+Fvto+x8Vk9sgMIAvz3jvPr22C7pwE69LJGt6GkYvK0wEYYg9J8V9bkJL8t 0FHe/XzJwao5hhMVsF47p7yiQe/8AKjPE7LupgQedqOYozDfPpChYmd066kAUcnTupOh xqOOQlJRDUz4s4zQAEQoAZUjSnqNZ/EBhAhEmgDxs6WAGIv0SwSljmcF0KHHaQyNexHu RVsQ== X-Gm-Message-State: AJcUukcYyf8SrxgnggVSNWNe4rvcQYY3JUp6X27dEdPMgJs8u9g7ATeb c0Hvg51oHUsh0ATcbH5hCsnzIB4d X-Google-Smtp-Source: ALg8bN5XZ3IBaDzH8QJBkh7u+q3aP3ppBSeTZjilUQdKIjPfLHOfQEul1oKCbO2O4wm/JkLogFQJFA== X-Received: by 2002:a1c:9e4a:: with SMTP id h71mr2405012wme.82.1546965013904; Tue, 08 Jan 2019 08:30:13 -0800 (PST) Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Alistair Francis , "Edgar E. Iglesias" , Eduardo Habkost , Marcel Apfelbaum , "Emilio G . Cota" Subject: [PATCH 2/4] qom/cpu: Add cluster_index to CPUState Date: Tue, 8 Jan 2019 16:30:06 +0000 Message-Id: <20190108163008.7006-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 For TCG we want to distinguish which cluster a CPU is in, and we need to do it quickly. Cache the cluster index in the CPUState struct, by having the cluster object set cpu->cluster_index for each CPU child when it is realized. This means that board/SoC code must add all CPUs to the cluster before realizing the cluster object. Regrettably QOM provides no way to prevent adding children to a realized object and no way for the parent to be notified when a new child is added to it, so we don't have any way to enforce/assert this constraint; all we can do is document it in a comment. The restriction on how many clusters can exist in the system is imposed by TCG code which will be added in a subsequent commit, but the check to enforce it in cluster.c fits better in this one. Signed-off-by: Peter Maydell --- include/hw/cpu/cluster.h | 19 +++++++++++++++++++ include/qom/cpu.h | 7 +++++++ hw/cpu/cluster.c | 33 +++++++++++++++++++++++++++++++++ qom/cpu.c | 1 + 4 files changed, 60 insertions(+) -- 2.19.2 Reviewed-by: Luc Michel diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 73818232437..d1bef315d10 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -34,12 +34,31 @@ * Arm big.LITTLE system) they should be in different clusters. If the CPUs do * not have the same view of memory (for example the main CPU and a management * controller processor) they should be in different clusters. + * + * A cluster is created by creating an object of TYPE_CPU_CLUSTER, and then + * adding the CPUs to it as QOM child objects (e.g. using the + * object_initialize_child() or object_property_add_child() functions). + * All CPUs must be added as children before the cluster is realized. + * (Regrettably QOM provides no way to prevent adding children to a realized + * object and no way for the parent to be notified when a new child is added + * to it, so this restriction is not checked for, but the system will not + * behave correctly if it is not adhered to.) + * + * A CPU which is not put into any cluster will be considered implicitly + * to be in a cluster with all the other "loose" CPUs, so all CPUs that are + * not assigned to clusters must be identical. */ #define TYPE_CPU_CLUSTER "cpu-cluster" #define CPU_CLUSTER(obj) \ OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) +/* + * This limit is imposed by TCG, which puts the cluster ID into an + * 8 bit field (and uses all-1s for the default "not in any cluster"). + */ +#define MAX_CLUSTERS 255 + /** * CPUClusterState: * @cluster_id: The cluster ID. This value is for internal use only and should diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 1396f53e5b5..844becbcedc 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -279,6 +279,11 @@ struct qemu_work_item; /** * CPUState: * @cpu_index: CPU index (informative). + * @cluster_index: Identifies which cluster this CPU is in. + * For boards which don't define clusters or for "loose" CPUs not assigned + * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will + * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER + * QOM parent. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. * @running: #true if CPU is currently running (lockless). @@ -404,6 +409,7 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; + int cluster_index; uint32_t halted; uint32_t can_do_io; int32_t exception_index; @@ -1109,5 +1115,6 @@ extern const struct VMStateDescription vmstate_cpu_common; #endif /* NEED_CPU_H */ #define UNASSIGNED_CPU_INDEX -1 +#define UNASSIGNED_CLUSTER_INDEX -1 #endif diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 9d50a235d5c..d672f54a620 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -20,19 +20,52 @@ #include "qemu/osdep.h" #include "hw/cpu/cluster.h" +#include "qom/cpu.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/cutils.h" static Property cpu_cluster_properties[] = { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), DEFINE_PROP_END_OF_LIST() }; +static void cpu_cluster_realize(DeviceState *dev, Error **errp) +{ + /* Iterate through all our CPU children and set their cluster_index */ + CPUClusterState *cluster = CPU_CLUSTER(dev); + ObjectPropertyIterator iter; + ObjectProperty *prop; + Object *cluster_obj = OBJECT(dev); + + if (cluster->cluster_id >= MAX_CLUSTERS) { + error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); + return; + } + + object_property_iter_init(&iter, cluster_obj); + while ((prop = object_property_iter_next(&iter))) { + Object *cpu_obj; + CPUState *cpu; + + if (!strstart(prop->type, "child<", NULL)) { + continue; + } + cpu_obj = object_property_get_link(cluster_obj, prop->name, NULL); + cpu = (CPUState *)object_dynamic_cast(cpu_obj, TYPE_CPU); + if (!cpu) { + continue; + } + cpu->cluster_index = cluster->cluster_id; + } +} + static void cpu_cluster_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->props = cpu_cluster_properties; + dc->realize = cpu_cluster_realize; } static const TypeInfo cpu_cluster_type_info = { diff --git a/qom/cpu.c b/qom/cpu.c index 5442a7323be..f5579b1cd50 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -364,6 +364,7 @@ static void cpu_common_initfn(Object *obj) CPUClass *cc = CPU_GET_CLASS(obj); cpu->cpu_index = UNASSIGNED_CPU_INDEX; + cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; /* *-user doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for softmmu */