From patchwork Fri Jan 18 14:58:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 155969 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3376582jaa; Fri, 18 Jan 2019 07:20:51 -0800 (PST) X-Google-Smtp-Source: ALg8bN75cMFIs4a/QXo1SwHyU9NvLiU9TnI4tUdGTHYe7JBKELwCkvBLa68sFtjJAC+iCLU904Ue X-Received: by 2002:adf:f0c5:: with SMTP id x5mr16360699wro.77.1547824851679; Fri, 18 Jan 2019 07:20:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547824851; cv=none; d=google.com; s=arc-20160816; b=mwdFUPpUo470Lp1xFcE0DUh/zhxFwjrI1OgFr1hyTvlk7niDiQAP3BUCRh+gRjWgwt snXBziU1TVxeosnX5cWlnsHtmpkR2R2l/p7KeUbTprV6YS6l3GY6rJmxn0u9itTUyxsJ EUKDqpgZAiA/VYQmadtSjPJ52ogfPfbSiu4/nbnQeV+CIqwSrM6kmHntBcVPSKN8PWKB OtbVip3wty9R/sZQYTb7bxqd5Meufi1tKqcGfr16btSpvMZbO0KeTBaHcaK6kmltnZr3 Ces4nsdLggQDof7FdjVDV2G6R9u9glevSmmfST9o0k5DYDmzXEVOZsC8l8i2Nb4jxCOi 2epg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Jowc/FBCz8XRY1StuJjoHUd6JspCGnmk9nEZdh98/eY=; b=k7YKF4ZLOQ/55DJvQnG9+AJLTd4JLbQuxGa/oDhr/TtijpmN2alghezmOTwZ6oX+MM oEVYFk29Hovse+Z6C38qkHu5sK/5zEBI1vqaNwleTaQcGXIlMDp2na+czxGNKAdDOEbA 8h2t5+F0heATX+cMjKnaGAYxIvDmgocsdAI7+UiogThvs2DDSDIf4QTaVXmureCyLI0u LVcLMIHyfsZkLGLESs75kfFbixuvKCb/9ROGPq11uJYxUiE0EASk+sY2L9nutrsP3IcN tV+FgtNIUluxlfryOJI1/eIR9Asw8dt+Q7n7ssPGH4IkCdJUPC2r+gGRhawiew4LXuTw gNVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DGBMHu00; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k14si37457587wrx.338.2019.01.18.07.20.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 18 Jan 2019 07:20:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DGBMHu00; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:41282 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkVww-0003AT-GB for patch@linaro.org; Fri, 18 Jan 2019 10:20:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkVc0-0003Ls-2U for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:59:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkVbu-0007oz-8J for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:59:12 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:38102) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gkVbt-0007n1-1p for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:59:06 -0500 Received: by mail-wm1-x32e.google.com with SMTP id m22so4811295wml.3 for ; Fri, 18 Jan 2019 06:59:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Jowc/FBCz8XRY1StuJjoHUd6JspCGnmk9nEZdh98/eY=; b=DGBMHu008W1+tcs+F6H9fAQXU2B2ZO+Ga2wv2cmghTNloDYMAqUk2Kxd6fIXxbE3u1 YArOMkc9wt5AolNuXt5soBl52kz32VqY0mbkW2K1/P8xVZjQz+3Tu5BMh2dYWXBy3vyp 4Fjq+1RszWk8+JA+GZ31wwZNilSVOYrFvcqdE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jowc/FBCz8XRY1StuJjoHUd6JspCGnmk9nEZdh98/eY=; b=ScyhNQLwGbOeKuP2WEsmdVSJ53FngR9Ez3Phxnsfpl8ylpzSG9//4iYLWll3hlFrmz IY1cGCb2vHwoIaKvx9PaDfgRPCnl+h51+e8pEgxGudeUv6TNTzEpBYU/L1qhxcalPkft Nlize3I1LdFHHkRfwnFFuJNFBb+BKGWuw8ulfLO2xwHpPu7+5WK9GrY7fuKiUsjmTJEn yib+QaBmtOq69GuXNFeuLwvMqnH3BuBYYNYY1uUszVECI16+xpwXTB9XXqSUXQ9x9mfl MqU/THSFtfoXYofQN5PNlb5Nn0Dng0T+u4vUASg89E7DwbZ9tDgPqyDuC6rzWH0/0+as nG3g== X-Gm-Message-State: AJcUukdL1xlsdCpiUCVl+jgPKVJMPuO9itXcym9SDWQ+0/I2goLrkW65 QNtA1XW025NfaseU/oKb65fWGAmhs2IMsQ== X-Received: by 2002:a1c:8acf:: with SMTP id m198mr16892239wmd.143.1547823543846; Fri, 18 Jan 2019 06:59:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.59.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:59:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:58:04 +0000 Message-Id: <20190118145805.6852-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 48/49] target/arm: Implement PMSWINC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-id: 20181211151945.29137-14-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 44f1340ee13..92666e52085 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1027,6 +1027,15 @@ static bool event_always_supported(CPUARMState *env) return true; } +static uint64_t swinc_get_count(CPUARMState *env) +{ + /* + * SW_INCR events are written directly to the pmevcntr's by writes to + * PMSWINC, so there is no underlying count maintained by the PMU itself + */ + return 0; +} + /* * Return the underlying cycle count for the PMU cycle counters. If we're in * usermode, simply return 0. @@ -1054,6 +1063,10 @@ static uint64_t instructions_get_count(CPUARMState *env) #endif static const pm_event pm_events[] = { + { .number = 0x000, /* SW_INCR */ + .supported = event_always_supported, + .get_count = swinc_get_count, + }, #ifndef CONFIG_USER_ONLY { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ .supported = instructions_supported, @@ -1393,6 +1406,24 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, pmu_op_finish(env); } +static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + unsigned int i; + for (i = 0; i < pmu_num_counters(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { + pmevcntr_op_start(env, i); + env->cp15.c14_pmevcntr[i]++; + pmevcntr_op_finish(env, i); + } + } +} + static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { uint64_t ret; @@ -1822,9 +1853,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), .writefn = pmovsr_write, .raw_writefn = raw_write }, - /* Unimplemented so WI. */ { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, - .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, + .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NO_RAW, + .writefn = pmswinc_write }, + { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, + .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NO_RAW, + .writefn = pmswinc_write }, { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),