From patchwork Fri Feb 1 16:06:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 157260 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp625370jaa; Fri, 1 Feb 2019 08:13:04 -0800 (PST) X-Google-Smtp-Source: AHgI3IZRI2UwtVJzJTmcjD/NDWJBKYRO2CGz9djzyxBZdckwOkToxDikCSPFVLlPP97ciAF0XUZy X-Received: by 2002:a25:bf91:: with SMTP id l17mr6673380ybk.197.1549037584059; Fri, 01 Feb 2019 08:13:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549037584; cv=none; d=google.com; s=arc-20160816; b=z3aCXyAxA/IrNgHXKJuek+Eu94hm6yCTgGfkSrNgLVcNWolz/u4Mlt6jj4oTuCvwIy 2C4qGKC+MtuVR8tagKj+aA3VFnTUGgywo1W29uJDPGLmwrCIbdq+5lZjeFX/YtFm231D wyHUGTCHoU+nl1i223EBaPG32xoJy41miww+NhBEWb8cCvLqxzVe+ebMporzdac6r03d Dj7lmWxYdzNA4FWE6O2z5fe+5uAHTlP0xONSpZ4R2mNJ+Z0LjsUKPFuPBfiS8MivuXdL 5l/E6zCvH0CMaJL8By2uTqclJarrXSOpqvK/KHgJBAmPfUgxM8JsuYLON5DPTED+ybb0 XW7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2xPzsoTxGIqinU+9lFGj/WnU9pSe/pbPfnUqFVkW8I0=; b=wWKmmQ1dxwj1M1afo9aLwooi+uRwEf8d5szMwGTBHasvmcwQNdOCorgSnSSoeZjSYI gGkzmDSjQmuy0kd+lag08aepExLtIrlMrOdW6dQebxlBHe6fBxJQCI74sQrQWEWkZEmt r2KlUszxW2H0PFhC3I63kKUUFZ4YzQ82bxJ0+GHtVFbmCw1U9A377Z96r6fvYgkTR8GV LfGaCyzUF8Sxtobz3c8yuLoz03OjuQxlH5F8HhO8H4uXil/0wGFNLOlSnEipsqG64Xdz 7IzhopFAIQAjvTJF8LAXeiLEdemVhl4ZnleB3cPvdjqTRfgUjvAqps26gqHcEuemjCpC gmYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IU1MopIY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v10si3397259ybm.405.2019.02.01.08.13.03 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 01 Feb 2019 08:13:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IU1MopIY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:57316 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gpbR9-00042z-CV for patch@linaro.org; Fri, 01 Feb 2019 11:13:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gpbM1-00085x-3i for qemu-devel@nongnu.org; Fri, 01 Feb 2019 11:07:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gpbLp-0003U6-4g for qemu-devel@nongnu.org; Fri, 01 Feb 2019 11:07:37 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:35365) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gpbLf-0003LG-I8 for qemu-devel@nongnu.org; Fri, 01 Feb 2019 11:07:27 -0500 Received: by mail-wm1-x344.google.com with SMTP id t200so6821097wmt.0 for ; Fri, 01 Feb 2019 08:07:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2xPzsoTxGIqinU+9lFGj/WnU9pSe/pbPfnUqFVkW8I0=; b=IU1MopIYcEr/fXlikaKBXrYrNSBqo/pAcfXFjuHf/8ueTDwcnTUHk5mrLzIvyuBSrW 1tfsVTlLHd1d5W1bAotlssYQzQ4NWnVno7inGtO8vLtPhrl2RvdwB1+afzXXSnpvFr/8 30+PfIrJUNLfDm+ry+BDG1vO8ca5Js9omYM/0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2xPzsoTxGIqinU+9lFGj/WnU9pSe/pbPfnUqFVkW8I0=; b=lEm7jbuiMGAiS3gtikEtAoKOYzzaUU2WiL6BRkQHJkpXdkFlPjcTMO/4ad3vLBRJbw lIpqrz77CdWqprlBDs7urSXpD8I9BA2psY2a0PQBa4ogqX3yPV1jvBmjCM2F/Rj/jpOQ XfhsK9MzCw+aMondbHQ7x69FY8d9JvSE4zHJ6xIDRqTDMV6BggXP80qS0I1ZCQ6EPc/g WNzQVM90iY6jMEGqnBIqzkQEGxlOxDgPDnvzjYRPAU6Yvr/gE2wV9dIpWUAfxscuZLN/ HDBV3d6T5sKKv5oq+CM6ppc2Lzq6GCHU1C21Uy/PGIaIKSFAPyqHhHn5tV6UrxFtO+5J zTgA== X-Gm-Message-State: AHQUAuYkQ8r0ltN+K0PaqJIw/EnVny+fLG4tiXT/PztUtq6vhW+TC7Dp 6W9M6pdvWhk6t+cg/LBDjBRAP0kKBAgDuA== X-Received: by 2002:a1c:4e08:: with SMTP id g8mr3001965wmh.46.1549037234805; Fri, 01 Feb 2019 08:07:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm2847250wmk.9.2019.02.01.08.07.13 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Feb 2019 08:07:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 1 Feb 2019 16:06:20 +0000 Message-Id: <20190201160653.13829-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org> References: <20190201160653.13829-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 14/47] hw/arm/armsse: Put each CPU in its own cluster object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190121185118.18550-14-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 2 ++ hw/arm/armsse.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 89f19a971f4..999c2e4f7e5 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -80,6 +80,7 @@ #include "hw/misc/iotkit-sysinfo.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" +#include "hw/cpu/cluster.h" #define TYPE_ARMSSE "arm-sse" #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE) @@ -110,6 +111,7 @@ typedef struct ARMSSE { /*< public >*/ ARMv7MState armv7m[SSE_MAX_CPUS]; + CPUClusterState cluster[SSE_MAX_CPUS]; IoTKitSecCtl secctl; TZPPC apb_ppc0; TZPPC apb_ppc1; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2472dfef3a1..2eb4ea3bfe0 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -147,9 +147,22 @@ static void armsse_init(Object *obj) memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); for (i = 0; i < info->num_cpus; i++) { - char *name = g_strdup_printf("armv7m%d", i); - sysbus_init_child_obj(obj, name, &s->armv7m[i], sizeof(s->armv7m), - TYPE_ARMV7M); + /* + * We put each CPU in its own cluster as they are logically + * distinct and may be configured differently. + */ + char *name; + + name = g_strdup_printf("cluster%d", i); + object_initialize_child(obj, name, &s->cluster[i], + sizeof(s->cluster[i]), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); + g_free(name); + + name = g_strdup_printf("armv7m%d", i); + sysbus_init_child_obj(OBJECT(&s->cluster[i]), name, + &s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7M); qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m33")); g_free(name); @@ -406,6 +419,18 @@ static void armsse_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } + /* + * The cluster must be realized after the armv7m container, as + * the container's CPU object is only created on realize, and the + * CPU must exist and have been parented into the cluster before + * the cluster is realized. + */ + object_property_set_bool(OBJECT(&s->cluster[i]), + true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);