From patchwork Fri Feb 1 16:06:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 157262 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp626307jaa; Fri, 1 Feb 2019 08:13:44 -0800 (PST) X-Google-Smtp-Source: ALg8bN4iv6oLi8UfaxQhZPo9bk4Mqz5RJ6bFeZdzYZZwlfcFqWJIkCnntpwMcCQWvDpwcuTpJ5yw X-Received: by 2002:a5b:546:: with SMTP id r6mr40547809ybp.174.1549037623991; Fri, 01 Feb 2019 08:13:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549037623; cv=none; d=google.com; s=arc-20160816; b=ifLmiJ/dunAHdnptzZ7kSdh2o5uZGVJuH4bQqIEIZUFFDPE5FHWC6vqEAwNxHrWyuN alwt09bc6mu0vVpS85LIeiyWf5iNgfIGkvY4bSm7WSlTxOn2BxecIYaW3l2yc8DAal9a piN996GpDZTp6d7hZbYozjKuMuYMsLJERtup8oP7prliXDDMS2xykhDvRERlwPqovuO3 JD5cW99aUlkRN0D3KOqg/de9fUhiVrBSOpR19hpFLZxKl7vpHVP+5iuGH9zHoG2zVFOF +xUWeIsxZ+8xNZltNCMNNwldeSAl04rc3t9SFCgUtMXg+6mjzwttKcpyyTzputqJ4g4T ltOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=xpufOzph+/xiAzd915jLBgo4M8irj3ScZHfTAI67nKE=; b=033MrFPQShrjab37ka2Q13zdV4XJBcsG3rp2UxRJZutwCZYXgvydiNBkEAGmAbDzOv JrpdoBmHD3d+53i/HGZFaFUNqJTM4VlNsy+DLdY1NC39E1A/tr4zVl0v6O1QovM540Vm yc0st1V682AJcjcUFMYFhGhdS41LL/OV/YB9X+YKHUwOc1whuNEJ4P2JdIjehNqIIRtK V3R2KhfxqF0mLxj4aX4K9CcQFB6nqTASEdPFPT779xyRqtTZ04K8Za9erKDI7laKxb0G AV9wb6fdgq/BXsduPf7o+43o7pstU+r2SNHxGkIFEyhtGTrYwShqQZ8OsjsOA8JFFWRA JI0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jVNkd3rs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d135si4605683ywa.100.2019.02.01.08.13.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 01 Feb 2019 08:13:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jVNkd3rs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:57322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gpbRn-0004ew-Ds for patch@linaro.org; Fri, 01 Feb 2019 11:13:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58888) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gpbMA-0008DX-Ol for qemu-devel@nongnu.org; Fri, 01 Feb 2019 11:07:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gpbM9-0003gT-2Q for qemu-devel@nongnu.org; Fri, 01 Feb 2019 11:07:54 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:46409) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gpbM7-0003Ny-8v for qemu-devel@nongnu.org; Fri, 01 Feb 2019 11:07:52 -0500 Received: by mail-wr1-x42f.google.com with SMTP id l9so7609362wrt.13 for ; Fri, 01 Feb 2019 08:07:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xpufOzph+/xiAzd915jLBgo4M8irj3ScZHfTAI67nKE=; b=jVNkd3rsyCWeTh6fTxrPo+xiGvZqLihO3K0AaN+5Um9AQHYPlq9qr0usC1OvXnifhi s2lumrovBtluyGt5/LI0mddQQAcaM7CbqxVY/EcwiKHMD//gvNjxdYyQSfJRSyUqwmpw Jgqi7/dqC57R3JIkRvfIGCm9N+xLqeWJOZRmg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xpufOzph+/xiAzd915jLBgo4M8irj3ScZHfTAI67nKE=; b=mWhQuCH1A3o6PvrlQD3ArA6tjEPMgk9HNP8BDxO/BLe6ZN30XpAkb5/OnEF0JPxWgF 53BG9xzxbYGBIx1F/5fMOFCxbdiq2foNSVwoX4FuN2/N0Z1zd+QlOxbXKr33e6YZxRUo oxoW7RqPMUbnUmbc8hdQl0DxlpamiQhWHRY+fn5qOzxQWGrs2LDeZChcPccZJdtjMtIu 4Fl/r7/uIC/YnS0UdPBXnFAweKz+vMBZkE/yK7ifmciuiANT3r0CV7/dpCRzTlK4Cjpp RE7y2EEkX8CaNasEZe6acLFxYsopp8P9p8Os1rn6gfw3mPwtKAxSm+oLQ2+NkGe8HFZq zw6Q== X-Gm-Message-State: AHQUAuZoQ1hwFr1JX+Z/+wxaDwl+aSf2T7FqeRA9/NA345q5CMauIywO rvMTaaLgIqsgw4tzjLdQJExx91KiWuG65A== X-Received: by 2002:a5d:4c82:: with SMTP id z2mr1061132wrs.252.1549037243593; Fri, 01 Feb 2019 08:07:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm2847250wmk.9.2019.02.01.08.07.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Feb 2019 08:07:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 1 Feb 2019 16:06:27 +0000 Message-Id: <20190201160653.13829-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org> References: <20190201160653.13829-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 21/47] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190121185118.18550-21-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 961dbb3032a..3914e8e4bf2 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -78,6 +78,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" +#include "hw/misc/armsse-cpuid.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" @@ -153,6 +154,8 @@ typedef struct ARMSSE { UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; + ARMSSECPUID cpuid[SSE_MAX_CPUS]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 9c111ac6a40..eb691faf720 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -34,6 +34,7 @@ struct ARMSSEInfo { bool has_ppus; bool has_cachectrl; bool has_cpusecctrl; + bool has_cpuid; }; static const ARMSSEInfo armsse_variants[] = { @@ -47,6 +48,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_ppus = false, .has_cachectrl = false, .has_cpusecctrl = false, + .has_cpuid = false, }, }; @@ -314,6 +316,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpuid) { + for (i = 0; i < info->num_cpus; i++) { + char *name = g_strdup_printf("cpuid%d", i); + + sysbus_init_child_obj(obj, name, &s->cpuid[i], + sizeof(s->cpuid[i]), + TYPE_ARMSSE_CPUID); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -864,6 +876,22 @@ static void armsse_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); } } + if (info->has_cpuid) { + for (i = 0; i < info->num_cpus; i++) { + MemoryRegion *mr; + + qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); + object_property_set_bool(OBJECT(&s->cpuid[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); + } + } /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ /* Devices behind APB PPC1: