diff mbox series

[PULL,29/47] target/arm/translate-a64: Don't underdecode add/sub extended register

Message ID 20190201160653.13829-30-peter.maydell@linaro.org
State Accepted
Commit 4f61106614410945b1d1c93081544ad5b13044fc
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell Feb. 1, 2019, 4:06 p.m. UTC 
In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20190125182626.9221-6-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

-- 
2.20.1
diff mbox series

Patch

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2cade64ed25..94907f0ae97 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4201,6 +4201,7 @@  static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
     int imm3 = extract32(insn, 10, 3);
     int option = extract32(insn, 13, 3);
     int rm = extract32(insn, 16, 5);
+    int opt = extract32(insn, 22, 2);
     bool setflags = extract32(insn, 29, 1);
     bool sub_op = extract32(insn, 30, 1);
     bool sf = extract32(insn, 31, 1);
@@ -4209,7 +4210,7 @@  static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
     TCGv_i64 tcg_rd;
     TCGv_i64 tcg_result;
 
-    if (imm3 > 4) {
+    if (imm3 > 4 || opt != 0) {
         unallocated_encoding(s);
         return;
     }