From patchwork Thu Feb 21 18:57:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 158945 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp847712jaa; Thu, 21 Feb 2019 11:12:55 -0800 (PST) X-Google-Smtp-Source: AHgI3IZ0AHjUWnxIbM2EQDiFEJuTQgy/9muaaOaO7YEbmN15sZHm85CxJtzvE7oaPCn5gCBCU20s X-Received: by 2002:a81:3c14:: with SMTP id j20mr75654ywa.324.1550776375635; Thu, 21 Feb 2019 11:12:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550776375; cv=none; d=google.com; s=arc-20160816; b=toVX20fAJEGpxKGneQXbp+WKYksw28cJdZaTXg6g+qwjC3ZilLwFIvVNU6c3TK3DM5 I1KYbsiP5Dk0u7C/4MXHgnC2A7cAT31Z/NwOEyL64JoS//4ZKHoLz4Al/O+JpIQnFeAD KhmIr863ko6NVmDBrpwHH7Iy7WD1OeMF9N5nw3qaQSRnZF5Zgz0tVVMc4cJyljeGmeyb mro4B51473T850FLXDtXCb0iX5znvuTv0MMokPEPlzwRuYuNheoJu/HKuFZt1ljIcD61 WvDdHjpUXnylMDqj6TzYrjbCGe+U3O+6DjWzz5a4DhwKEy6Q9p/acWsXmOcnQld+yA4c 2yfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CV0XuO7Jmju7b92elRHfSbeU/noy4D/dxWzQMm7SpKg=; b=fOsAzPbWyZYnvoEeIeVMYoKgf0v9+Weq4wkEcCc3zSuRrkzcZGiIxInk4wDUMSxVwq LOIi/QglIjRr0GxESJuW20OtM3Q/VP/Ygj+toF9uX2u57VslgvrqOsuffhSIYsm+5/Ra t8ltDjkIdkRE72XXq8WkFz179bXWsTH9w38gTg3y8cwrNZx2jQL1O+FYw4yqI5tOUA3b canvTVpUWdToPv0E2XNr/0km+xKbIdWL/FSqAZk2XFMo4rMPIxNn4+j4G4xtcOEhAZ6E tdLwzEm4ehKefjw/5pNiUhBtv7thYGJ1ImuTuAAOFZgnSszazSxCRhcH/ve3lJAawibU HJ8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LjkCOz6T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o200si7644283ywd.287.2019.02.21.11.12.55 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 21 Feb 2019 11:12:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LjkCOz6T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:37074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwtmB-0004e2-2S for patch@linaro.org; Thu, 21 Feb 2019 14:12:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwtXq-0008UB-Nm for qemu-devel@nongnu.org; Thu, 21 Feb 2019 13:58:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gwtXp-0007SX-3N for qemu-devel@nongnu.org; Thu, 21 Feb 2019 13:58:06 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36612) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gwtXo-0007Nr-HG for qemu-devel@nongnu.org; Thu, 21 Feb 2019 13:58:04 -0500 Received: by mail-wm1-x343.google.com with SMTP id j125so10314088wmj.1 for ; Thu, 21 Feb 2019 10:57:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CV0XuO7Jmju7b92elRHfSbeU/noy4D/dxWzQMm7SpKg=; b=LjkCOz6T+XgqaFiCPz0iM+efAj/5H4jwwW7ipWg05MP3ZttOP65tlnVyIkVTK712lZ T6zZpPuuCyCOEN1Wkixu3aLiGpzl0J9fkGR6pc9FryPmfWjhUPCx9cAqs9s7Q0IIxYIU TROwgnnfPrw0XgwYg6s3mdNuQPQFlfFaruF5O6lL0bOaIZDL8T1ZOKhpn5H6TFqj2oZZ oF2FSVNfo8tiR7pU2JJKTrOiOAsplWoRaVfj1KVZyUBihRMxn/It80PYRW1r4tVi0kL7 zQp1r5S+91wNYXb4kdSirCB2WHrThVvE0uenebB0AZH+FcHoCSk6eEwHAVeSQrxp4Rxr Z08Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CV0XuO7Jmju7b92elRHfSbeU/noy4D/dxWzQMm7SpKg=; b=K2j/3+tofi13NrebmchB04UP2FMSA6RldpX4Pp8oBOwcy0Snkw3N8fNHT0bGwQL4XA Q78oqIxyv/USsdu515q51V1lCGS9tyleO9EDmcYUkfd95kR8K618FRQ5gnPXM2psqwzM rtjyglGfQvbxsYxhNFZQmbhPcdWp15kstnow0yumn2kvpDe1yQJjlqKocqr+aVcPMJM6 4gZBEKQCiy26CgtnlKqIeVehGkV1e4ga7uXgUyRXGkuq2M8r8JGNADFEdf+pOI3AtKU2 N0LclK8nIw2lb4iF5YHohuIaXdq8CVHlTrQ/6uRImdh1yFk+9XrzLLf0IbdQOAur7YAz iuCw== X-Gm-Message-State: AHQUAubgtCdGKoTjSFeyShOWiUhxXxZ7hGztxkrHoXqxGbETJlywngQa CJXmdhGVTZoggxhENt+yTlpUvEZ7BT0= X-Received: by 2002:a1c:c282:: with SMTP id s124mr11158899wmf.105.1550775477726; Thu, 21 Feb 2019 10:57:57 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm29065085wre.32.2019.02.21.10.57.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 10:57:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 21 Feb 2019 18:57:30 +0000 Message-Id: <20190221185739.25362-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221185739.25362-1-peter.maydell@linaro.org> References: <20190221185739.25362-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 12/21] hw/char/pl011: Support all interrupt lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The PL011 UART has six interrupt lines: * RX (receive data) * TX (transmit data) * RT (receive timeout) * MS (modem status) * E (errors) * combined (logical OR of all the above) So far we have only emulated the combined interrupt line; add support for the others, so that boards that wire them up to different interrupt controller inputs can do so. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/char/pl011.h | 2 +- hw/char/pl011.c | 46 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 45 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index 1b52bfd5c90..dad3cf29121 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -45,7 +45,7 @@ typedef struct PL011State { int read_count; int read_trigger; CharBackend chr; - qemu_irq irq; + qemu_irq irq[6]; const unsigned char *id; } PL011State; diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 0c4711e4027..29f4e5eb224 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -7,6 +7,17 @@ * This code is licensed under the GPL. */ +/* + * QEMU interface: + * + sysbus MMIO region 0: device registers + * + sysbus IRQ 0: UARTINTR (combined interrupt line) + * + sysbus IRQ 1: UARTRXINTR (receive FIFO interrupt line) + * + sysbus IRQ 2: UARTTXINTR (transmit FIFO interrupt line) + * + sysbus IRQ 3: UARTRTINTR (receive timeout interrupt line) + * + sysbus IRQ 4: UARTMSINTR (momem status interrupt line) + * + sysbus IRQ 5: UARTEINTR (error interrupt line) + */ + #include "qemu/osdep.h" #include "hw/char/pl011.h" #include "hw/sysbus.h" @@ -22,18 +33,46 @@ #define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_RXFE 0x10 +/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ +#define INT_OE (1 << 10) +#define INT_BE (1 << 9) +#define INT_PE (1 << 8) +#define INT_FE (1 << 7) +#define INT_RT (1 << 6) +#define INT_TX (1 << 5) +#define INT_RX (1 << 4) +#define INT_DSR (1 << 3) +#define INT_DCD (1 << 2) +#define INT_CTS (1 << 1) +#define INT_RI (1 << 0) +#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) +#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) + static const unsigned char pl011_id_arm[8] = { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] = { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; +/* Which bits in the interrupt status matter for each outbound IRQ line ? */ +static const uint32_t irqmask[] = { + INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ + INT_RX, + INT_TX, + INT_RT, + INT_MS, + INT_E, +}; + static void pl011_update(PL011State *s) { uint32_t flags; + int i; flags = s->int_level & s->int_enabled; trace_pl011_irq_state(flags != 0); - qemu_set_irq(s->irq, flags != 0); + for (i = 0; i < ARRAY_SIZE(s->irq); i++) { + qemu_set_irq(s->irq[i], (flags & irqmask[i]) != 0); + } } static uint64_t pl011_read(void *opaque, hwaddr offset, @@ -284,10 +323,13 @@ static void pl011_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); PL011State *s = PL011(obj); + int i; memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000); sysbus_init_mmio(sbd, &s->iomem); - sysbus_init_irq(sbd, &s->irq); + for (i = 0; i < ARRAY_SIZE(s->irq); i++) { + sysbus_init_irq(sbd, &s->irq[i]); + } s->read_trigger = 1; s->ifl = 0x12;