From patchwork Wed Apr 3 03:43:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161662 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2517920jan; Tue, 2 Apr 2019 20:56:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqyrEeSR2NBw4/CEGpjYZXMBmXwBGS1RKG36mEKqcOB+Vcv2YN/+eJYom7GvhO0q2q9SZ6dm X-Received: by 2002:a25:504e:: with SMTP id e75mr12788445ybb.68.1554263776950; Tue, 02 Apr 2019 20:56:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263776; cv=none; d=google.com; s=arc-20160816; b=rFXqqvX0J6qLbpQFkzSU8ujMLPfkJThVpTr61oIGzDX+WMNUnuWOcyX296/jlixB9k kyUuc9BjMxI5Ay5FoV8+SzAEoqOit/2oSyCjMk7xHVJDBm6BAHySQGYyJbV/O2eTix2W cZ6iTkJxBn26iDmyfhTiumuNZsOnqtUUV/cNF9N5VBVC3Vk80NOcadQPZv8UBp9GjyXH OC6Y5Q5Sp8r4dkPv7wItMwCL73mpXwMtkqESRFNOXe2QJ1EyiYFvKsX3jbLq4RVIhOrh G0CyOffjf4CgqvBTfg8vX54E1Z8tpEpPV8l/jsKXy5lp2+1K/i4w4lkrw2J3Ag1//Ndw Zqdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=UklP9VelN2cs0kBnRd6fHc4X8KepPl0VqL+sEcPMx0Q=; b=xpwbUdTY7Bu03GfAFH3TM49KQbiz6U7+mMm9gceWIOE/K9a1ukVFhVlT4aLBzJxlDf Ypt9wsy1Z4O1+05U3ti2MqVhsKf+WyiQiEu+I+lzW5s4feQmir95NXQvO2pmZw50tRy6 RZe2nn24l419qF+CLXuR6na6CudN5UeO6PNg0VOyFnzjkXIKox80vpHnMthDmHgDC5XL HLOT9Oa5TtDYQiyhRoqz5acn7DHEB78r1mnLnRgegCYvFEPyyOQPTz67ePXuhhjHFfmy WFyfmUvNOJ0zjkNNbBlak3KQn+z6cJ9KEvSr88yUlnMU6kV4KT87rPnwCSmMo3u40e7a WH/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=j9mJfA9S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a4si10209210ywm.13.2019.04.02.20.56.16 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 02 Apr 2019 20:56:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=j9mJfA9S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:54203 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBX0a-0004wO-F8 for patch@linaro.org; Tue, 02 Apr 2019 23:56:16 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48786) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWpQ-000382-Qu for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWpP-0000CR-6j for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:44 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:33027) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWpO-0000Bt-Rm for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:43 -0400 Received: by mail-pf1-x442.google.com with SMTP id i19so7434372pfd.0 for ; Tue, 02 Apr 2019 20:44:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UklP9VelN2cs0kBnRd6fHc4X8KepPl0VqL+sEcPMx0Q=; b=j9mJfA9SKq0pdaj0FOszB1RfIcrm9YUqyo6x3bhZMw0nCORnhOkd+hQ4KCp0+hXLu3 UqzCF4ilEgIsvsaw6OOmg3TUeYJMHJlAZCDVh8/9cG/LXfFRZhwia8UmRV4YZQM0iDuu 8WPXpWO3jvoxxpARUhye7L9OSI+/63M6Tso8s/KRtUNaBPEPW6DzQrEcRlWx7zaxaDhc lfkbnJYsNiVUODI91YDP5CwLqgmnJwuQMtIas321Xshf3oehoPt735vw347ftZrAfjfi Sl/VCunCROO5eO91luyQgkufoV0pO9oUwgLx7lnhZyqZOjtpSr6DCvmu9OATegnHLMND 73nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UklP9VelN2cs0kBnRd6fHc4X8KepPl0VqL+sEcPMx0Q=; b=W3hgjXb5OrVXQxQa6buv60v8+SOQtxpiIkoBWEop8DbF6WYMgm6/eip+H4KjCsDfXS /fYb1uaTUTFuMvCwS4JFyBJYnU9RKJsV6XvjwoZ1kKXDzdS/5M9i43uEmQD9/wahCW8p Mp1Fk7ilfhcdLQ2wgqXZc7GmDzoZFtEXKaxHqguzw3Y5xRY6VVb/Wk1vhNwd+Ojqizbx gDgqO2iG3Yl8NVoBpxVM7n4NW1LqxTgCODBt5cofWVRnWRA+XuPdvZvUGdCLo1wdRUgs jk/Qp05H/MfhS3SWnn5ba2ybPn0WzHEtYszLRyKp/PLfZsRn4O/zwY/kNyzdj5q/HBqD oT+A== X-Gm-Message-State: APjAAAUoAWBF+R6gnGkov6mOUDjS76GSQ3A5wICH8A2ycGYp1Uo2rOkm mqwipoDkwLvjnWHeORkxuuQU5Pn/sM4PJw== X-Received: by 2002:a63:5a1d:: with SMTP id o29mr66018630pgb.320.1554263081638; Tue, 02 Apr 2019 20:44:41 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:51 +0700 Message-Id: <20190403034358.21999-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 19/26] target/sparc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Artyom Tarasenko Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 5 +- target/sparc/cpu.c | 5 +- target/sparc/ldst_helper.c | 15 ---- target/sparc/mmu_helper.c | 175 +++++++++++++++++++------------------ 4 files changed, 93 insertions(+), 107 deletions(-) -- 2.17.1 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4972ebcfd4..44336e5899 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -580,8 +580,9 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); /* mmu_helper.c */ -int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4a4445bdf5..016a70717e 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -880,9 +880,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; cc->gdb_read_register = sparc_cpu_gdb_read_register; cc->gdb_write_register = sparc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault; -#else + cc->tlb_fill = sparc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access = sparc_cpu_unassigned_access; cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 5bc090213c..88196a3ad9 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1924,19 +1924,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, #endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = sparc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - cpu_loop_exit_restore(cs, retaddr); - } -} #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 135a9c9d9b..b0fdabbea3 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -24,28 +24,7 @@ /* Sparc MMU emulation */ -#if defined(CONFIG_USER_ONLY) - -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - if (rw & 2) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] = address; -#else - env->mmuregs[4] = address; -#endif - } - return 1; -} - -#else +#ifndef CONFIG_USER_ONLY #ifndef TARGET_SPARC64 /* @@ -85,10 +64,10 @@ static const int perm_table[2][8] = { } }; -static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, - target_ulong address, int rw, int mmu_idx, - target_ulong *page_size) +static int get_physical_address1(CPUSPARCState *env, hwaddr *physical, + int *prot, int *access_index, + target_ulong address, int rw, int mmu_idx, + target_ulong *page_size) { int access_perms = 0; hwaddr pde_ptr; @@ -206,51 +185,41 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, return error_code; } -/* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +static int get_physical_address(CPUSPARCState *env, hwaddr *physical, + int *prot, int *access_index, + target_ulong address, int rw, int mmu_idx, + target_ulong *page_size) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - hwaddr paddr; - target_ulong vaddr; - target_ulong page_size; - int error_code = 0, prot, access_index; + int error_code; + CPUState *cs = CPU(sparc_env_get_cpu(env)); - address &= TARGET_PAGE_MASK; - error_code = get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - vaddr = address; - if (error_code == 0) { - qemu_log_mask(CPU_LOG_MMU, - "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " - TARGET_FMT_lx "\n", address, paddr, vaddr); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + error_code = get_physical_address1(env, physical, prot, access_index, + address, rw, mmu_idx, page_size); + + if (error_code && ((env->mmuregs[0] & MMU_NF) || env->psret == 0)) { + /* + * No fault mode: if a mapping is available, just override + * permissions. If no mapping is available, redirect accesses to + * neverland. Fake/overridden mappings will be flushed when + * switching to normal mode. + */ + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return 0; } if (env->mmuregs[3]) { /* Fault status register */ env->mmuregs[3] = 1; /* overflow (not read before another fault) */ } - env->mmuregs[3] |= (access_index << 5) | error_code | 2; + env->mmuregs[3] |= (*access_index << 5) | error_code | 2; env->mmuregs[4] = address; /* Fault address register */ - if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { - /* No fault mode: if a mapping is available, just override - permissions. If no mapping is available, redirect accesses to - neverland. Fake/overridden mappings will be flushed when - switching to normal mode. */ - prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + if (rw & 2) { + cs->exception_index = TT_TFAULT; } else { - if (rw & 2) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; - } - return 1; + cs->exception_index = TT_DFAULT; } + + return error_code; } target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) @@ -711,34 +680,6 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, } } -/* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - target_ulong vaddr; - hwaddr paddr; - target_ulong page_size; - int error_code = 0, prot, access_index; - - address &= TARGET_PAGE_MASK; - error_code = get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - if (error_code == 0) { - vaddr = address; - - trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, - env->dmmu.mmu_primary_context, - env->dmmu.mmu_secondary_context); - - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; - } - /* XXX */ - return 1; -} - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env) { unsigned int i; @@ -865,3 +806,63 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } #endif + +/* Perform address translation */ +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + +#ifdef CONFIG_USER_ONLY + if (access_type == MMU_INST_FETCH) { + cs->exception_index = TT_TFAULT; + } else { + cs->exception_index = TT_DFAULT; + } +# ifdef TARGET_SPARC64 + env->dmmu.mmuregs[4] = address; +# else + env->mmuregs[4] = address; +# endif +#else + hwaddr paddr; + target_ulong vaddr; + target_ulong page_size; + int error_code = 0, prot, access_index; + + address &= TARGET_PAGE_MASK; + error_code = get_physical_address(env, &paddr, &prot, &access_index, + address, access_type, mmu_idx, + &page_size); + vaddr = address; + if (error_code == 0) { +# ifdef TARGET_SPARC64 + trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, + env->dmmu.mmu_primary_context, + env->dmmu.mmu_secondary_context); +# else + qemu_log_mask(CPU_LOG_MMU, + "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " + TARGET_FMT_lx "\n", address, paddr, vaddr); +# endif + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + return true; + } + + if (probe) { + return false; + } +#endif + + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif