From patchwork Fri May 10 20:00:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163951 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp2819407ilr; Fri, 10 May 2019 13:06:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqy4vIm0aF/Srru5pl5484P/i5x3pqj8b829+j7uKPSyvCVfuk/1xVYVScj1WHV3V87zXVst X-Received: by 2002:a50:95af:: with SMTP id w44mr13370936eda.95.1557518770856; Fri, 10 May 2019 13:06:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557518770; cv=none; d=google.com; s=arc-20160816; b=pe38UWJjVCMyROStEzhpEmkaDmGx/KcYXxXoxHbeK2U8EW2QGAHvDAYKpMj5JBUI5U 8ZiKUtDvJmN3Eh0Hkeiu6wQl/waWFinVz/kg6sj4nPTz9Yf6PGuHLDZH7QaEc0QHwTXr gTF2iMAbQ9Mh0vWX9lINye5tQE6v5ApTPGs/qczspn9gF4ZOgkYd1kXAfCHuMyzWMvzN CkZtfIXowbBc4pSrlx03jKVVWBkDietQE4sA4HXjx3OWJbmYuQQ7R8uR9052SvN6lCFA uoxVlpc+xcf3Gv7sjXLlH3h8ZZj1g4cOU8YSilU60QB3hsmfO8kAchNvTND6ZExXAafm bgUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2jRFCM+GPqo8vu/j1Bzu3XKh2Bvye2YGkMc6M6eXRGI=; b=ojNLK34GhpAFwiTtFIsuo0SypfIxwPTIAGw1AawQUaXoheGMpKg5H7iMBqg4kqGiG5 8U86vt+oPCyC1M4P+tATZTqy1vESE9GwQFah2eIsrA6pTjWwv3pQ2oYvRmZCFWSV0M+u v6KCJzFZlWNDN05pqbIV5qjdXlin9J6bZm9rAnda0P2hsh8C3SUoq3tczy6MIdE8CYu/ 4m3jwPBavLrc+bJP2kVbhCKSAh+edQsdrr/s1JyJn4Ec4fm3zYfP5i+3CtkwPQGcd1Xe WMiB1dGxjrH6spmdkCgqC6awsqvmR3tPDlHohJsD8hF/xJ/y4zFll+GGiihn+98dVSMJ BuDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=r7rcIN8g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d20si170927eda.159.2019.05.10.13.06.10 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 10 May 2019 13:06:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=r7rcIN8g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:49347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hPBmT-0006Tl-Lm for patch@linaro.org; Fri, 10 May 2019 16:06:09 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hPBhk-0002SE-KD for qemu-devel@nongnu.org; Fri, 10 May 2019 16:01:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hPBhi-0002V6-1m for qemu-devel@nongnu.org; Fri, 10 May 2019 16:01:16 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:35262) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hPBhd-0002OD-Sh for qemu-devel@nongnu.org; Fri, 10 May 2019 16:01:11 -0400 Received: by mail-wm1-x32e.google.com with SMTP id q15so4593544wmj.0 for ; Fri, 10 May 2019 13:01:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2jRFCM+GPqo8vu/j1Bzu3XKh2Bvye2YGkMc6M6eXRGI=; b=r7rcIN8gz/AAQGBl6XwVxMMRHzeRto+c+l5pUscHfJYSwn5TAmru/biwi0N7WgPKR9 HJDNVART7BjP7o4G4BezRN4vy+Fr+8is3tWe5Y+Chpu8++2AejceiCQwhFAWB5VYNNpM tfc9u5fowCi2CWNaK4c09jPuO+rpSTTMKZbedUeKU+GB88Lfbq3a50WuaLkTVA5wYQei iuhVNj/Sx1Bge3pl2hAkmL+1sha2sH/Xph60yoNX3UbClBcgmi6cCwCveFekVtN/H5Hk AeRxw51HWeUiu+KJViCgOhd6Bcssizfmh3gHeZ1nTj8yAVRjRPzOjxDCyeLI32ZgNqz0 pCcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2jRFCM+GPqo8vu/j1Bzu3XKh2Bvye2YGkMc6M6eXRGI=; b=RF8O4EtM8b17cHe8nqnkSXxQeW1EDy5RZtDDsdbqJseuL10RLhqcHH8V/hTwlpw/gi gIswdHFTKUQw4+dd2unM70NEBO9MZaRR91OWvhHJ3tG00+X9b3nOYvWWdCzd8A/9XTlM D9C4+wZe6l3NPFx/PqtgxUWwThM98yGRYzt025F88S1jLTxzkHOpfP0sX/+xqX5pbD/0 S2D/8nkBSi6Rluow6Ht8NTQWWak+qnOckVoCN5W9fUVvsGqNUZe8u7eA6H8cDNz2Eq+X ETatroB7bIIUtY0DYhm1+Jt81eV33eFevkO4THL8SB020Dy3PxwJmwadtHXd/gPuU1hx ylWw== X-Gm-Message-State: APjAAAVv2204dfjR1f9/XiXSDaOgulcwmYdZoihL/JwEvXEgnpWBeZ3S A+Inl2YTYzyoidT/kTu2omyuDg== X-Received: by 2002:a1c:9e04:: with SMTP id h4mr8671879wme.135.1557518464549; Fri, 10 May 2019 13:01:04 -0700 (PDT) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id s13sm3139414wrw.17.2019.05.10.13.01.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 10 May 2019 13:01:03 -0700 (PDT) Received: from zen.linaroharston. (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 047DA1FF8F; Fri, 10 May 2019 21:01:02 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 10 May 2019 21:00:58 +0100 Message-Id: <20190510200101.31096-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190510200101.31096-1-alex.bennee@linaro.org> References: <20190510200101.31096-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 2/5] cputlb: Move TLB_RECHECK handling into load/store_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Mark Cave-Ayland , qemu-devel@nongnu.org, Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Having this in io_readx/io_writex meant that we forgot to re-compute index after tlb_fill. It also means we can use the normal aligned memory load path. It also fixes a bug in that we had cached a use of index across a tlb_fill. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée Tested-by: Mark Cave-Ayland -- 2.20.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 12f21865ee7..9c04eb1687c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -856,9 +856,8 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) } static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, - int mmu_idx, - target_ulong addr, uintptr_t retaddr, - bool recheck, MMUAccessType access_type, int size) + int mmu_idx, target_ulong addr, uintptr_t retaddr, + MMUAccessType access_type, int size) { CPUState *cpu = ENV_GET_CPU(env); hwaddr mr_offset; @@ -868,30 +867,6 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; - if (recheck) { - /* - * This is a TLB_RECHECK access, where the MMU protection - * covers a smaller range than a target page, and we must - * repeat the MMU check here. This tlb_fill() call might - * longjump out if this access should cause a guest exception. - */ - CPUTLBEntry *entry; - target_ulong tlb_addr; - - tlb_fill(cpu, addr, size, access_type, mmu_idx, retaddr); - - entry = tlb_entry(env, mmu_idx, addr); - tlb_addr = (access_type == MMU_DATA_LOAD ? - entry->addr_read : entry->addr_code); - if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { - /* RAM access */ - uintptr_t haddr = addr + entry->addend; - - return ldn_p((void *)haddr, size); - } - /* Fall through for handling IO accesses */ - } - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -925,9 +900,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, } static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, - int mmu_idx, - uint64_t val, target_ulong addr, - uintptr_t retaddr, bool recheck, int size) + int mmu_idx, uint64_t val, target_ulong addr, + uintptr_t retaddr, int size) { CPUState *cpu = ENV_GET_CPU(env); hwaddr mr_offset; @@ -936,30 +910,6 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; - if (recheck) { - /* - * This is a TLB_RECHECK access, where the MMU protection - * covers a smaller range than a target page, and we must - * repeat the MMU check here. This tlb_fill() call might - * longjump out if this access should cause a guest exception. - */ - CPUTLBEntry *entry; - target_ulong tlb_addr; - - tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); - - entry = tlb_entry(env, mmu_idx, addr); - tlb_addr = tlb_addr_write(entry); - if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { - /* RAM access */ - uintptr_t haddr = addr + entry->addend; - - stn_p((void *)haddr, size, val); - return; - } - /* Fall through for handling IO accesses */ - } - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -1218,14 +1168,15 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, target_ulong tlb_addr = code_read ? entry->addr_code : entry->addr_read; const size_t tlb_off = code_read ? offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read); + const MMUAccessType access_type = + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD; unsigned a_bits = get_alignment_bits(get_memop(oi)); void *haddr; uint64_t res; /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, - code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, + cpu_unaligned_access(ENV_GET_CPU(env), addr, access_type, mmu_idx, retaddr); } @@ -1234,8 +1185,7 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, addr & TARGET_PAGE_MASK)) { tlb_fill(ENV_GET_CPU(env), addr, size, - code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, - mmu_idx, retaddr); + access_type, mmu_idx, retaddr); index = tlb_index(env, mmu_idx, addr); entry = tlb_entry(env, mmu_idx, addr); } @@ -1244,17 +1194,33 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - uint64_t tmp; - if ((addr & (size - 1)) != 0) { goto do_unaligned_access; } - tmp = io_readx(env, iotlbentry, mmu_idx, addr, retaddr, - tlb_addr & TLB_RECHECK, - code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, size); - return handle_bswap(tmp, size, big_endian); + if (tlb_addr & TLB_RECHECK) { + /* + * This is a TLB_RECHECK access, where the MMU protection + * covers a smaller range than a target page, and we must + * repeat the MMU check here. This tlb_fill() call might + * longjump out if this access should cause a guest exception. + */ + tlb_fill(ENV_GET_CPU(env), addr, size, + access_type, mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); + + tlb_addr = code_read ? entry->addr_code : entry->addr_read; + tlb_addr &= ~TLB_RECHECK; + if (!(tlb_addr & ~TARGET_PAGE_MASK)) { + /* RAM access */ + goto do_aligned_access; + } + } + + res = io_readx(env, &env->iotlb[mmu_idx][index], mmu_idx, addr, + retaddr, access_type, size); + return handle_bswap(res, size, big_endian); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1281,8 +1247,8 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, return res & MAKE_64BIT_MASK(0, size * 8); } + do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); - switch (size) { case 1: res = ldub_p(haddr); @@ -1446,15 +1412,33 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - if ((addr & (size - 1)) != 0) { goto do_unaligned_access; } - io_writex(env, iotlbentry, mmu_idx, + if (tlb_addr & TLB_RECHECK) { + /* + * This is a TLB_RECHECK access, where the MMU protection + * covers a smaller range than a target page, and we must + * repeat the MMU check here. This tlb_fill() call might + * longjump out if this access should cause a guest exception. + */ + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); + + tlb_addr = tlb_addr_write(entry); + tlb_addr &= ~TLB_RECHECK; + if (!(tlb_addr & ~TARGET_PAGE_MASK)) { + /* RAM access */ + goto do_aligned_access; + } + } + + io_writex(env, &env->iotlb[mmu_idx][index], mmu_idx, handle_bswap(val, size, big_endian), - addr, retaddr, tlb_addr & TLB_RECHECK, size); + addr, retaddr, size); return; } @@ -1502,8 +1486,8 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } + do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); - switch (size) { case 1: stb_p(haddr, val);