From patchwork Tue Jun 4 20:33:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 165839 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp6346533ili; Tue, 4 Jun 2019 13:55:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqw4Gn5FMcNpj8suBE+UGOpoeIM/2cl4omHLls8hEwRHyaenuxNb57KeodscQ8TGKWCToAGu X-Received: by 2002:a67:8d03:: with SMTP id p3mr18278933vsd.190.1559681711687; Tue, 04 Jun 2019 13:55:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559681711; cv=none; d=google.com; s=arc-20160816; b=dvWJRGNtmoA38rnvKfZkj23WnZiAShH+pN2L5cXAeVy+i3C5RfreOjspoUKDqjd0X6 0pcy8GA/vHyQh5/q32q+W9ilvWHIctwcXDYzeoU0MQ2l76le4lB+t3rpBSr/Uufax81b m3MyW9xcUTYjqZxKh9gnXuXV+H3u7HBepoDqbJa44gMFxIPWfLnnHeyH8HUFsv87tCMt jLyym3Ek6lYsltiDDlUJbu275DyhrCGrTlAq5QzYUGnqejIiBdyfOBs2oyCNzuBlY9dm BMXj6wr3FxIUDZj23qcIUIe98/cDl2jV3531j3avge/6lEI8UkSB6xoFX43meRGL7Pbt sXbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Iz2EvZFIABjNbnkyC3UNjG2s6yNlDWo5TqN7+5GSNOs=; b=UlaX4Gk5rIqIWWbmCVOoSUJ1rnkfoHkS3QS1Bh7dUMUWsGDhG+POS5d+UPgw0tx61c k+1YGs5CJps2PkDwpVDPvN3SIffk1AXkyS/RfHP/WXM+m6Szn4dhSl5SjbNp8twMwUs3 9xgdU3MhrvYfFm6lXAgKH2UZ37C2CcTAbYUhmctzrdv3ZMeh01mhZR4ALfJM+icr0jty zl//Qk3aF3qgc6+xPNYPOSa8baUxyQ5dDSlOPzPxNbehyGoP4/Tlh3zA1aqVhP/XmQI6 4AHjzMzMGA3PaOIvRLZQsW3iSN1sCzsmh0Yfr1mD0zvK60EbyQhcqrFgA6MEHVKOgkzq kmhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dfatdokm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g1si1963160vsa.36.2019.06.04.13.55.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 04 Jun 2019 13:55:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dfatdokm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:57892 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGSd-0001zT-67 for patch@linaro.org; Tue, 04 Jun 2019 16:55:11 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG94-0001hs-Te for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:35:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG93-00050s-G1 for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:58 -0400 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:33686) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG91-0004rm-Gk for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:57 -0400 Received: by mail-ot1-x344.google.com with SMTP id p4so4024739oti.0 for ; Tue, 04 Jun 2019 13:34:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=Iz2EvZFIABjNbnkyC3UNjG2s6yNlDWo5TqN7+5GSNOs=; b=dfatdokm9TB3x/9etBxCYS6//ddPBSOkTFuV2/9BVeEkCwIt96RYqU7eeFPpRKewOu h6JP1Vko+6UiBUDHtwlFesVK9X2zknjqagphNdZZugDkxkk+39TNs3sJ2VPRT4hvBoFP 7Z2YvCeFj6ACEqeI588CI5UkfN0ZGnB0wmUl3mG5wOvde/CMSneDhA50kHq/BKFWwNWK vLB+4TqjRYDpuC+xR2xdudiuzDwqnbaDVlIhKNllUKhw785FJcHQa+MZLOtrV8HGcZLF 42wYOth1CIv0QBxPU4FHMeo2PMIvk7wWYE5qwLG80BTPj9XgUk63cZK1lTsEs/B8E40M WbyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Iz2EvZFIABjNbnkyC3UNjG2s6yNlDWo5TqN7+5GSNOs=; b=KLs3t4GbDiA6+OxFe9z4HwFF/2QgnR89+w9Jf5Aup4p77DpOQOPDJuUhua624zXsI4 BrFVJck2XZF0Ahsq2pPq5WS/ephkEMre7fVHdlbMl8RLVJvzlK8twB807HdOry8q6HF/ Dtm/+9D3TEe8TKEDdrWcUFX4uvWk7EI1jDHJnfrfeS80T53z2uwgmp70WIOoYOljR2AP fZhfSmytz1Z0L0f5JY8rwkU7a+Zdm3xZmgOZhXu03HW+ovgwWmW69GCy2UglvfNDXtuK Yp/cZvnvcw+nQq16mgwbFdax8YrN9lVXYsvvukdiQvDouCzES3yn46q7rI8EEiphMeb7 UJMw== X-Gm-Message-State: APjAAAWNheJD2zh8DTmWqby0cRwYIm6oaEFjWXz/+7j6jkTlD2lsb47J HH7uAg6+przlDorrxATmmudJzr03a3kDsQ== X-Received: by 2002:a05:6830:1050:: with SMTP id b16mr1746988otp.228.1559680491501; Tue, 04 Jun 2019 13:34:51 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:49 -0500 Message-Id: <20190604203351.27778-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 37/39] tcg/aarch64: Use LDP to load tlb mask+table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This changes the code generation for the tlb from e.g. ldur x0, [x19, #0xffffffffffffffe0] ldur x1, [x19, #0xffffffffffffffe8] and x0, x0, x20, lsr #8 add x1, x1, x0 ldr x0, [x1] ldr x1, [x1, #0x18] to ldp x0, x1, [x19, #-0x20] and x0, x0, x20, lsr #8 add x1, x1, x0 ldr x0, [x1] ldr x1, [x1, #0x18] Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- v3: Add QEMU_BUILD_BUG_ON for mask/table ordering; comment fixes. --- tcg/aarch64/tcg-target.inc.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 57c297f9d7..b0f8106642 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1641,6 +1641,10 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); +/* These offsets are built into the LDP below. */ +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8); + /* Load and compare a TLB entry, emitting the conditional jump to the slow path for the failure case, which will be patched later when finalizing the slow path. Generated code returns the host addend in X1, @@ -1649,23 +1653,20 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits = get_alignment_bits(opc); unsigned s_bits = opc & MO_SIZE; unsigned a_mask = (1u << a_bits) - 1; unsigned s_mask = (1u << s_bits) - 1; - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0, x3; + TCGReg x3; TCGType mask_type; uint64_t compare_mask; mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, mask_type, TCG_REG_X0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, table_base, table_ofs); + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); /* Extract the TLB index from the address into X0. */ tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64,