From patchwork Tue Jun 11 10:53:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 166399 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2212818ilk; Tue, 11 Jun 2019 04:11:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqzqWhnnECCwgbAktXcNyinUum+lx0S14uHPP92YDcS/KdeqX6ZtV2uYfUdvk6gZVM3/pAUu X-Received: by 2002:a0c:d24d:: with SMTP id o13mr8678756qvh.86.1560251464123; Tue, 11 Jun 2019 04:11:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560251464; cv=none; d=google.com; s=arc-20160816; b=UiPqOF8qHDD28TPFoz/nAvbtFQHL8rJlBHJHeJ8JNRXA3XQu77IE00s4Hpg1XC1fCo jlguHbfiZE3iTi1eqZccFTlYylfX9FSYqUUFHlMYS1b/h1cyZnlOVd+UN7aauguYDJWb rg5H9MQuC8tf/uaRrJhP09/8LzThBB6J+3AtQ8HJM0lskjivJ4ip/RCroEixzhDOsmXn xQQB0WUfO2tjs5p7vGBVcuNZ+ggtuIo3DBbngqdqcZ3rK2eD2adOzpDQjuTjd4ikAX8O 7tQhwExncdgutICoYslRb6JOKQfURhaw425YvqWxwGPn47z0ZVJamyZy4LLvP4FQFFpW a8ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=eNBmWZIm97TjmvwdrXNoqxnA5CbE2nGaaTGyw39+1hQ=; b=jpNYU4zki8r/T9Vw+SkeBTqsyvuoDlgDJeQExfDd1r2TJNM4ACTfzZuRMC0GU7tGVh 4Cg5xW/2x3KxuTvNSjpX7M0MkJIrm5Nr8eScIwXpdEHWMv45RW6jS28mqm+LZcZTsAvf ugWxdiv7pi+Mvzc2imJOCSbPs31tnyrkE/hkTn9xnLzV11L8gBLptVpjRDd92RJ2QeL9 cmY5HeM3TsEDpwfMUK/EcRIfXLet3wZEffE9bw2t6pvzwQe//DHE/ZATZ1W4o/Qtd2jx Yzv9nqJj0hIaKj/8C2s+Rm9zxwSDoVFTFE9ZNyfuw901XmBLNQk0GvyEn3nl+AEWLps5 QDAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GeVgCSSr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h90si587801qva.0.2019.06.11.04.11.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 11 Jun 2019 04:11:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GeVgCSSr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56292 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1haegB-0005Yh-MO for patch@linaro.org; Tue, 11 Jun 2019 07:11:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39113) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1haePu-0007Dg-JS for qemu-devel@nongnu.org; Tue, 11 Jun 2019 06:54:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1haePr-0007OM-BG for qemu-devel@nongnu.org; Tue, 11 Jun 2019 06:54:14 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:50487) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1haePp-0007Jp-7R for qemu-devel@nongnu.org; Tue, 11 Jun 2019 06:54:09 -0400 Received: by mail-wm1-x341.google.com with SMTP id c66so2435558wmf.0 for ; Tue, 11 Jun 2019 03:54:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eNBmWZIm97TjmvwdrXNoqxnA5CbE2nGaaTGyw39+1hQ=; b=GeVgCSSrJwgGKnMbAnoCMdGxfXYsgbTA3poOHyG2jWs+p3uqLi92pWtE61FijJ+wil BCmYmDpnjqD+dKytPC5wy7wSUI363stV9Q9BjSf3/zyTe+7b1YaLDSDklZm/arABRWjh muUDRP+7d7Uq4q+9byBHFzmP21O9n68N6NDivBe7elrMrY5pHXa9XoTw/2o/Xy33IVTs YroBQfdXwfZBidmi7W1aGwdPCrhEE1CrxDVCONcCvYeKXx7XcZzYDZgaREtbDrr42D6f M/MRkZZguuJchZ8h7ao65QReIm8hJFirk2ppFIaSjZizFOymO1wYXx7LCbXwZwW9MkqX yxdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eNBmWZIm97TjmvwdrXNoqxnA5CbE2nGaaTGyw39+1hQ=; b=LnaO48udcQhKjg8dOy551GP0EQczXkK/ThZe2OGMsv+y+slrHnjKvxSLNSDm863Phr 6GdH1AVRZKin7pNXLd9g6Xxb27XSQfL2CGvKqWwSNU1UZVJx5afp/8nASrJsym7e1slh WsRUi8ByJorIKGH9KinXD+hhCLW528NbU4dh7sDmkA+ksAGDgH0LybpqVI9+2YGGgZfm 6+9cMn5bAZ2geFmKnyyj8M+8pLLTkxs+wmsGj7Of1JlMgQpEOxMBmhKhh0FZzc+zqewV W/QwdgDFUeG+DZvs7q1kWuY7VVYgiVoEcuQmkUoQ5f4rpjHlE9ZBUO42EfvDG1r7cUTQ QP/g== X-Gm-Message-State: APjAAAXpGYrqu6Lhepf4GvHwyEiT5lYHmecE4DmCycAE08qET+dNH2tF ++uI39to+mwuD4wEo3kzDU9xAA== X-Received: by 2002:a1c:ed01:: with SMTP id l1mr17977485wmh.109.1560250445478; Tue, 11 Jun 2019 03:54:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e17sm10785945wrt.95.2019.06.11.03.54.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 03:54:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 11 Jun 2019 11:53:20 +0100 Message-Id: <20190611105351.9871-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190611105351.9871-1-peter.maydell@linaro.org> References: <20190611105351.9871-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v2 11/42] target/arm: Add helpers for VFP register loads and stores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- target/arm/translate.c | 10 +++++++++ 2 files changed, 30 insertions(+), 20 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 2f070a6e0d9..24358f3d3eb 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -179,8 +179,8 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_gen_ext_i32_i64(nf, cpu_NF); tcg_gen_ext_i32_i64(vf, cpu_VF); - tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg64(frn, rn); + neon_load_reg64(frm, rm); switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, @@ -207,7 +207,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_temp_free_i64(tmp); break; } - tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg64(dest, rd); tcg_temp_free_i64(frn); tcg_temp_free_i64(frm); tcg_temp_free_i64(dest); @@ -226,8 +226,8 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) frn = tcg_temp_new_i32(); frm = tcg_temp_new_i32(); dest = tcg_temp_new_i32(); - tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg32(frn, rn); + neon_load_reg32(frm, rm); switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, @@ -254,7 +254,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_temp_free_i32(tmp); break; } - tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg32(dest, rd); tcg_temp_free_i32(frn); tcg_temp_free_i32(frm); tcg_temp_free_i32(dest); @@ -298,14 +298,14 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) frm = tcg_temp_new_i64(); dest = tcg_temp_new_i64(); - tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg64(frn, rn); + neon_load_reg64(frm, rm); if (vmin) { gen_helper_vfp_minnumd(dest, frn, frm, fpst); } else { gen_helper_vfp_maxnumd(dest, frn, frm, fpst); } - tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg64(dest, rd); tcg_temp_free_i64(frn); tcg_temp_free_i64(frm); tcg_temp_free_i64(dest); @@ -316,14 +316,14 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) frm = tcg_temp_new_i32(); dest = tcg_temp_new_i32(); - tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg32(frn, rn); + neon_load_reg32(frm, rm); if (vmin) { gen_helper_vfp_minnums(dest, frn, frm, fpst); } else { gen_helper_vfp_maxnums(dest, frn, frm, fpst); } - tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg32(dest, rd); tcg_temp_free_i32(frn); tcg_temp_free_i32(frm); tcg_temp_free_i32(dest); @@ -379,9 +379,9 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) TCGv_i64 tcg_res; tcg_op = tcg_temp_new_i64(); tcg_res = tcg_temp_new_i64(); - tcg_gen_ld_f64(tcg_op, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg64(tcg_op, rm); gen_helper_rintd(tcg_res, tcg_op, fpst); - tcg_gen_st_f64(tcg_res, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg64(tcg_res, rd); tcg_temp_free_i64(tcg_op); tcg_temp_free_i64(tcg_res); } else { @@ -389,9 +389,9 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) TCGv_i32 tcg_res; tcg_op = tcg_temp_new_i32(); tcg_res = tcg_temp_new_i32(); - tcg_gen_ld_f32(tcg_op, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg32(tcg_op, rm); gen_helper_rints(tcg_res, tcg_op, fpst); - tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg32(tcg_res, rd); tcg_temp_free_i32(tcg_op); tcg_temp_free_i32(tcg_res); } @@ -440,14 +440,14 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) tcg_double = tcg_temp_new_i64(); tcg_res = tcg_temp_new_i64(); tcg_tmp = tcg_temp_new_i32(); - tcg_gen_ld_f64(tcg_double, cpu_env, vfp_reg_offset(1, rm)); + neon_load_reg64(tcg_double, rm); if (is_signed) { gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); } else { gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); } tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); - tcg_gen_st_f32(tcg_tmp, cpu_env, vfp_reg_offset(0, rd)); + neon_store_reg32(tcg_tmp, rd); tcg_temp_free_i32(tcg_tmp); tcg_temp_free_i64(tcg_res); tcg_temp_free_i64(tcg_double); @@ -455,13 +455,13 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) TCGv_i32 tcg_single, tcg_res; tcg_single = tcg_temp_new_i32(); tcg_res = tcg_temp_new_i32(); - tcg_gen_ld_f32(tcg_single, cpu_env, vfp_reg_offset(0, rm)); + neon_load_reg32(tcg_single, rm); if (is_signed) { gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst); } else { gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); } - tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(0, rd)); + neon_store_reg32(tcg_res, rd); tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_single); } diff --git a/target/arm/translate.c b/target/arm/translate.c index e42a21d4aa5..3661ed57cd3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1689,6 +1689,16 @@ static inline void neon_store_reg64(TCGv_i64 var, int reg) tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); } +static inline void neon_load_reg32(TCGv_i32 var, int reg) +{ + tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); +} + +static inline void neon_store_reg32(TCGv_i32 var, int reg) +{ + tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); +} + static TCGv_ptr vfp_reg_ptr(bool dp, int reg) { TCGv_ptr ret = tcg_temp_new_ptr();