diff mbox series

[PULL,10/48] target/arm: Fix Cortex-R5F MVFR values

Message ID 20190613121433.5246-11-peter.maydell@linaro.org
State Not Applicable
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell June 13, 2019, 12:13 p.m. UTC 
The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.20.1
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4d5d46db7f0..c8441fc07b7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1609,6 +1609,8 @@  static void cortex_r5f_initfn(Object *obj)
 
     cortex_r5_initfn(obj);
     set_feature(&cpu->env, ARM_FEATURE_VFP3);
+    cpu->isar.mvfr0 = 0x10110221;
+    cpu->isar.mvfr1 = 0x00000011;
 }
 
 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {