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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8D6121FF8C; Wed, 31 Jul 2019 17:07:19 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 31 Jul 2019 17:06:26 +0100 Message-Id: <20190731160719.11396-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190731160719.11396-1-alex.bennee@linaro.org> References: <20190731160719.11396-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v4 01/54] target/arm: handle M-profile semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , aaron@os.amperecomputing.com, cota@braap.org, "open list:ARM TCG CPUs" , bobby.prani@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do this for other semihosting calls so we might as well do it for M-profile as well. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/m_helper.c | 18 ++++++------------ target/arm/translate.c | 20 +++++++++++++++++++- 2 files changed, 25 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 84609f446e6..129d52a56bf 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2113,19 +2113,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) break; } break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] = do_arm_semihosting(env); + return; case EXCP_BKPT: - if (semihosting_enabled()) { - int nr; - nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; - if (nr == 0xab) { - env->regs[15] += 2; - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); - env->regs[0] = do_arm_semihosting(env); - return; - } - } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 7853462b21b..0b02c520395 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10976,6 +10976,24 @@ illegal_op: default_exception_el(s)); } +/* + * Thumb BKPT. On M-profile CPUs this may be a semihosting call which + * we can process much the same way as gen_hlt() above. + */ +static inline void gen_thumb_bkpt(DisasContext *s, int imm8) +{ + if (arm_dc_feature(s, ARM_FEATURE_M) && + semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + s->current_el != 0 && +#endif + (imm8 == 0xab)) { + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); + return; + } + gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true)); +} + static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rn, rd, shift, cond; @@ -11611,7 +11629,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) { int imm8 = extract32(insn, 0, 8); ARCH(5); - gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true)); + gen_thumb_bkpt(s, imm8); break; }