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[209.51.188.17]) by mx.google.com with ESMTPS id q39si16726436qtk.133.2019.09.04.14.51.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 14:51:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:40534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5dBj-0001dF-Ru for patch@linaro.org; Wed, 04 Sep 2019 17:51:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53833) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cCu-0001Dm-Bh for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5cCt-00023E-27 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:48 -0400 Received: from 7.mo7.mail-out.ovh.net ([46.105.43.131]:45247) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5cCr-00020n-UH for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:46 -0400 Received: from player691.ha.ovh.net (unknown [10.108.54.36]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 0F36D130B4B for ; Wed, 4 Sep 2019 22:48:42 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player691.ha.ovh.net (Postfix) with ESMTPSA id D498398B2998; Wed, 4 Sep 2019 20:48:34 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 22:46:57 +0200 Message-Id: <20190904204659.13878-14-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904204659.13878-1-clg@kaod.org> References: <20190904204659.13878-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2533556269348457233 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejhedgudehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.43.131 Subject: [Qemu-devel] [RFC PATCH 13/15] aspeed: Parameterise number of MACs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley To support the ast2600's four MACs allow SoCs to specify the number they have, and create that many. Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 5 ++++- hw/arm/aspeed_soc.c | 7 ++++++- 2 files changed, 10 insertions(+), 2 deletions(-) -- 2.21.0 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 74db48374531..30b67a09f13c 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -30,7 +30,7 @@ #define ASPEED_SPIS_NUM 2 #define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 -#define ASPEED_MACS_NUM 2 +#define ASPEED_MACS_NUM 4 typedef struct AspeedSoCState { /*< private >*/ @@ -67,6 +67,7 @@ typedef struct AspeedSoCInfo { uint64_t sram_size; int spis_num; int wdts_num; + int macs_num; const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; @@ -117,6 +118,8 @@ enum { ASPEED_I2C, ASPEED_ETH1, ASPEED_ETH2, + ASPEED_ETH3, + ASPEED_ETH4, ASPEED_SDRAM, ASPEED_XDMA, }; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 80d7f206004c..8069de8d5a36 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -90,7 +90,9 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_SPI1] = 0x1E630000, [ASPEED_SPI2] = 0x1E641000, [ASPEED_ETH1] = 0x1E660000, + [ASPEED_ETH3] = 0x1E670000, [ASPEED_ETH2] = 0x1E680000, + [ASPEED_ETH4] = 0x1E690000, [ASPEED_VIC] = 0x1E6C0000, [ASPEED_SDMC] = 0x1E6E0000, [ASPEED_SCU] = 0x1E6E2000, @@ -190,6 +192,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .sram_size = 0x8000, .spis_num = 1, .wdts_num = 2, + .macs_num = 2, .irqmap = aspeed_soc_ast2400_irqmap, .memmap = aspeed_soc_ast2400_memmap, .num_cpus = 1, @@ -200,6 +203,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .sram_size = 0x9000, .spis_num = 2, .wdts_num = 3, + .macs_num = 2, .irqmap = aspeed_soc_ast2500_irqmap, .memmap = aspeed_soc_ast2500_memmap, .num_cpus = 1, @@ -210,6 +214,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .sram_size = 0x10000, .spis_num = 2, .wdts_num = 4, + .macs_num = 4, .irqmap = aspeed_soc_ast2600_irqmap, .memmap = aspeed_soc_ast2600_memmap, .num_cpus = 2, @@ -305,7 +310,7 @@ static void aspeed_soc_init(Object *obj) OBJECT(&s->scu), &error_abort); } - for (i = 0; i < ASPEED_MACS_NUM; i++) { + for (i = 0; i < sc->info->macs_num; i++) { sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); }