From patchwork Wed Sep 25 14:32:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 174360 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp732166ill; Wed, 25 Sep 2019 07:46:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqxhrlSBMTRNaN8xDJr3DDPc6VDRCzrhvj6QcJKS0eQ3LNRPKf9SDIidBxGDuTQeAN0uTfLQ X-Received: by 2002:a17:906:bc2:: with SMTP id y2mr4539941ejg.148.1569422764749; Wed, 25 Sep 2019 07:46:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569422764; cv=none; d=google.com; s=arc-20160816; b=qsBH1HKeD+Xw431iQhH76Bi4JLfzF/bQKFnzN1HtbkveXoYAbFErWUqlDRkQXiicfy DVZ8M40gUWDvycLkFS55xSCNEq61I6fnhA7kyRe64WkLHN6jIG18VrtBGV0auzEG76Zb Ax2gQh8jfiVWdxxKo7pGkTgdy6jqSGGem5ObO586yM94kuj831ZY4WPhW3huOdlStUiU gqMhomPoxvhgXz5JXEnAHyU9JLle50bf8O/ZtqMXUYM235xTWxxTeK/wVV1FhRrEGdq1 yByGlELrb52HODp0EAnfbWSOpZ4ssK2zWcvSI/NG9kUS+rrgGFAN4zzE0aTrqeghcpKO 45PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=HqK9ZOyy3V0AxDgazCHhqpgdABGg960M9d1gT3ShylE=; b=so3wyGtHORwH5mPjqZhylW1eLdos5uH4ZYgHKP+MvNbeN4QWI9PowTZiMSdh3F2Vh6 ImKbt1gDEOs5Y5UXZBsRuUM8ZgW2KWCgvePCzv7U2vU9UDEPA2HdMu/ygCb3KJKp7szX Vy0lFO2eNrub05z2Y5gOqN1blWw3WLd6KJ/Y8sc+FeESHxIlOZxbnD3I++MoEHcjgqij aZyhPmYPV0jUNE4qQLV/Io+H6ddN8b+JcJNHWXnoLKHFj/aH5YfEyyE/bGGl9bvVEDKE rEIOrVnNmE4/yr723nq8JLUBADiu0ZIN8B8sfX2O6yCRQ4EX0gtmYfhUQX2m9718mOcv nbvA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a8si3887607edm.240.2019.09.25.07.46.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 07:46:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:53094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD8YM-00070S-UN for patch@linaro.org; Wed, 25 Sep 2019 10:46:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52536) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD8Mu-0003uy-0f for qemu-devel@nongnu.org; Wed, 25 Sep 2019 10:34:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iD8Mr-00015x-Gc for qemu-devel@nongnu.org; Wed, 25 Sep 2019 10:34:11 -0400 Received: from 6.mo68.mail-out.ovh.net ([46.105.63.100]:53471) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iD8Mr-00013G-7L for qemu-devel@nongnu.org; Wed, 25 Sep 2019 10:34:09 -0400 Received: from player786.ha.ovh.net (unknown [10.108.54.74]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id F071514317A for ; Wed, 25 Sep 2019 16:34:06 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player786.ha.ovh.net (Postfix) with ESMTPSA id 65145A4D3E7A; Wed, 25 Sep 2019 14:34:00 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Subject: [PATCH v2 09/23] aspeed/sdmc: Add AST2600 support Date: Wed, 25 Sep 2019 16:32:34 +0200 Message-Id: <20190925143248.10000-10-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190925143248.10000-1-clg@kaod.org> References: <20190925143248.10000-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8853513918268672785 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrfedvgdejkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.63.100 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley The AST2600 SDMC controller is slightly different from its predecessor (DRAM training). Max memory is now 2G on the AST2600. Signed-off-by: Joel Stanley [clg: - improved commit log - reworked model integration into new object class ] Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_sdmc.h | 1 + hw/misc/aspeed_scu.c | 2 + hw/misc/aspeed_sdmc.c | 82 +++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) -- 2.21.0 diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h index 81156320c497..5dbde59fe777 100644 --- a/include/hw/misc/aspeed_sdmc.h +++ b/include/hw/misc/aspeed_sdmc.h @@ -15,6 +15,7 @@ #define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC) #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" +#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600" #define ASPEED_SDMC_NR_REGS (0x174 >> 2) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 84699b78d4ce..717509bc5460 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -99,6 +99,7 @@ #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) #define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) +#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) #define AST2600_HPLL_PARAM TO_REG(0x200) #define AST2600_HPLL_EXT TO_REG(0x204) #define AST2600_MPLL_EXT TO_REG(0x224) @@ -602,6 +603,7 @@ static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, + [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */ [AST2600_HPLL_PARAM] = 0x1000405F, }; diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 60c99e773488..f3a63a2e01db 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -28,6 +28,7 @@ /* Control/Status Register #1 (ast2500) */ #define R_STATUS1 (0x60 / 4) #define PHY_BUSY_STATE BIT(0) +#define PHY_PLL_LOCK_STATUS BIT(4) #define R_ECC_TEST_CTRL (0x70 / 4) #define ECC_TEST_FINISHED BIT(12) @@ -85,6 +86,11 @@ #define ASPEED_SDMC_AST2500_512MB 0x2 #define ASPEED_SDMC_AST2500_1024MB 0x3 +#define ASPEED_SDMC_AST2600_256MB 0x0 +#define ASPEED_SDMC_AST2600_512MB 0x1 +#define ASPEED_SDMC_AST2600_1024MB 0x2 +#define ASPEED_SDMC_AST2600_2048MB 0x3 + #define ASPEED_SDMC_AST2500_READONLY_MASK \ (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ @@ -186,6 +192,28 @@ static int ast2500_rambits(AspeedSDMCState *s) return ASPEED_SDMC_AST2500_512MB; } +static int ast2600_rambits(AspeedSDMCState *s) +{ + switch (s->ram_size >> 20) { + case 256: + return ASPEED_SDMC_AST2600_256MB; + case 512: + return ASPEED_SDMC_AST2600_512MB; + case 1024: + return ASPEED_SDMC_AST2600_1024MB; + case 2048: + return ASPEED_SDMC_AST2600_2048MB; + default: + break; + } + + /* use a common default */ + warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M", + s->ram_size); + s->ram_size = 512 << 20; + return ASPEED_SDMC_AST2600_512MB; +} + static void aspeed_sdmc_reset(DeviceState *dev) { AspeedSDMCState *s = ASPEED_SDMC(dev); @@ -340,11 +368,65 @@ static const TypeInfo aspeed_2500_sdmc_info = { .class_init = aspeed_2500_sdmc_class_init, }; +static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) +{ + uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | + ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | + ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s)); + + /* Make sure readonly bits are kept (use ast2500 mask) */ + data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; + + return data | fixed_conf; +} + +static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, + uint32_t data) +{ + switch (reg) { + case R_CONF: + data = aspeed_2600_sdmc_compute_conf(s, data); + break; + case R_STATUS1: + /* Will never return 'busy'. 'lock status' is always set */ + data &= ~PHY_BUSY_STATE; + data |= PHY_PLL_LOCK_STATUS; + break; + case R_ECC_TEST_CTRL: + /* Always done, always happy */ + data |= ECC_TEST_FINISHED; + data &= ~ECC_TEST_FAIL; + break; + default: + break; + } + + s->regs[reg] = data; +} + +static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); + + dc->desc = "ASPEED 2600 SDRAM Memory Controller"; + asc->max_ram_size = 2048 << 20; + asc->compute_conf = aspeed_2600_sdmc_compute_conf; + asc->write = aspeed_2600_sdmc_write; +} + +static const TypeInfo aspeed_2600_sdmc_info = { + .name = TYPE_ASPEED_2600_SDMC, + .parent = TYPE_ASPEED_SDMC, + .class_init = aspeed_2600_sdmc_class_init, +}; + static void aspeed_sdmc_register_types(void) { type_register_static(&aspeed_sdmc_info); type_register_static(&aspeed_2400_sdmc_info); type_register_static(&aspeed_2500_sdmc_info); + type_register_static(&aspeed_2600_sdmc_info); } type_init(aspeed_sdmc_register_types);