From patchwork Mon Oct 14 16:03:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176304 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp4746731ill; Mon, 14 Oct 2019 09:42:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqyNluzzPbucGWXy1L5VR+39/e7f9CI02v3VL1xs5K3aSdwgOSlTRXFF52M35wh7x6GDAATD X-Received: by 2002:a17:906:950e:: with SMTP id u14mr29665562ejx.145.1571071361675; Mon, 14 Oct 2019 09:42:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571071361; cv=none; d=google.com; s=arc-20160816; b=s+zJRNaTZdmVmpGgEiUo02Gi8kdLxe+kog20I9Na1J7+L1K/9uDrVLMlkl9DASzTRT hAjEvp8eYDULl6jEgDsd5624ItkBkptKn6BVDOHjf4db4BnebHMHJ1c+kM6PxoJZxHMy 8c9oUin7bEU0+adRx+Nvw8T3Td/1EjuHdoBAI2QuMrwY6uxcA5rqHVzdjQrnwtw9deYT CTL1XbOh8v4tC0nO0BPW1dXNcRFa/0GYxepJaClYtRaod7K6NJjVwcZzTqxLg2l4JQV/ Ox79QtA7MMkbUoM/x7EO6gA29dW5eVW2u1ATa41fmkLmBf8hY5YlzXtH1OzP2SGAYgb8 ns7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vP5GcYuUE/pjFlJ1lHMM9Tj7/XDRmZl7iSdxbfoBULU=; b=wSLHYifyJC+4XzUGadluN4qYNXZYoJd6EbnRM1eSqs79IQd0VVJRdeYngwDZ8ICWD0 EYgdv2ph5/Okr/1vrKrziWFJliZig0wlsJIadzBg3WTvoGcBFxLmm2KW3OUIrD0R3C7H kPsUX/JvhijoqRBotTp8cOcXACWQtszQXn7ZM2ccdidRCtWNVM8RcljTkSQAhj7KPGze D3xSWNpoizo8WQotjnjYV40Y+KLKtylkJ2/xf6P1cT/8+XX+sVOB0+g3eTs8RpxPPFRt +/KuNtdIhm7ps3j9rAajxT2679UgCv0JyZj/1FYFHRA1Ukwcc82zZVmRXqCSdqKrqQaK 5uMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="IawZ/1jH"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v20si11241064edq.195.2019.10.14.09.42.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 Oct 2019 09:42:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="IawZ/1jH"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iK3Qe-0002mC-G2 for patch@linaro.org; Mon, 14 Oct 2019 12:42:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37418) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iK2ql-0005Id-WB for qemu-devel@nongnu.org; Mon, 14 Oct 2019 12:05:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iK2qj-00089a-Do for qemu-devel@nongnu.org; Mon, 14 Oct 2019 12:05:35 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:37682) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iK2qj-00088Z-6h for qemu-devel@nongnu.org; Mon, 14 Oct 2019 12:05:33 -0400 Received: by mail-wr1-x42c.google.com with SMTP id p14so20382536wro.4 for ; Mon, 14 Oct 2019 09:05:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vP5GcYuUE/pjFlJ1lHMM9Tj7/XDRmZl7iSdxbfoBULU=; b=IawZ/1jHhf+PIor81+rbQZyJRuxezJJesef1df1fpTP7BLt/iaIYC+BXJy3ya2enzj Qy8JrHQy5HnhcQJYos0ltNW76TT1xV7tdhMjw6UuYg3JooYfiL736fsH35xl3uyROUdc afT4bWOMqrhRh9ubNgHvZg/BC/SjbLpXTmmGUZcW2MWOxYFw0a1pkJW76J0rPqT4heoN lucnDFIIPDN0nuPK7KflJWEzyhvfzBVvvGAki7nbVjFQ/Ss+SxMApXJ8AiOS31A5+ncS WTxBe80yuOn7E1W1Ljm4N7ug8z/QOVF+4TM1s95l+TbEzS+asr2Q3r7rAMTxo1uAEazy y2+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vP5GcYuUE/pjFlJ1lHMM9Tj7/XDRmZl7iSdxbfoBULU=; b=dtLg+cQpJ13lMJpSoVxXwQIilZfGtbA2Lu0K6ZO+EJN/2P/RQO8U8Das1wVVmfCcB+ XV+al9yCHjUIU5jpB2G0puioFL4UxclzhiaCYPCnvCzVsmlEbQ8dPzvy5h4MWi2p157n RfUek0KATbzYdOgN0dzIERF/Dq2JsvnnCMxD3qHe8KMupAtx3WIzebX+7ut8WDr9hFZ7 A1veYeus1SQ0MDuWplT8uMn8AfuoNiM4g2E1xQ5sXOWsFx7RrxnuujaMtcW7Tsw7RSpf eIVNvSupmDV4Lm5eF1/OxA5uaUDFBXG0N4ggAqe7Z5Q5YE8onW1yhymheKpTDRYdkORW wpPg== X-Gm-Message-State: APjAAAVNZRGuwjkuUp37g/teibkMRilW9V1pI2aqhL+KXaAomUTOsUvm CptPQGLSK64lMfPc2xMtpJDkNqsgoyyxPA== X-Received: by 2002:adf:e2c5:: with SMTP id d5mr12606072wrj.283.1571069130845; Mon, 14 Oct 2019 09:05:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 5sm18029779wrk.86.2019.10.14.09.05.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2019 09:05:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 54/68] aspeed/i2c: Introduce an object class per SoC Date: Mon, 14 Oct 2019 17:03:50 +0100 Message-Id: <20191014160404.19553-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191014160404.19553-1-peter.maydell@linaro.org> References: <20191014160404.19553-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater It prepares ground for register differences between SoCs. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20190925143248.10000-16-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/i2c/aspeed_i2c.h | 15 ++++++++++ hw/arm/aspeed_soc.c | 3 +- hw/i2c/aspeed_i2c.c | 60 ++++++++++++++++++++++++++++++++----- 3 files changed, 69 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index a2753f0bbba..6e2dae7db81 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -25,6 +25,8 @@ #include "hw/sysbus.h" #define TYPE_ASPEED_I2C "aspeed.i2c" +#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" +#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" #define ASPEED_I2C(obj) \ OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C) @@ -59,6 +61,19 @@ typedef struct AspeedI2CState { AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; } AspeedI2CState; +#define ASPEED_I2C_CLASS(klass) \ + OBJECT_CLASS_CHECK(AspeedI2CClass, (klass), TYPE_ASPEED_I2C) +#define ASPEED_I2C_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AspeedI2CClass, (obj), TYPE_ASPEED_I2C) + +typedef struct AspeedI2CClass { + SysBusDeviceClass parent_class; + + uint8_t num_busses; + uint8_t reg_size; + uint8_t gap; +} AspeedI2CClass; + I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr); #endif /* ASPEED_I2C_H */ diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 5c5fcb81094..e60f198d92c 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -188,8 +188,9 @@ static void aspeed_soc_init(Object *obj) object_property_add_const_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), &error_abort); + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), - TYPE_ASPEED_I2C); + typename); snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index a956eb38492..fabdb01e974 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -408,10 +408,11 @@ static void aspeed_i2c_reset(DeviceState *dev) { int i; AspeedI2CState *s = ASPEED_I2C(dev); + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); s->intr_status = 0; - for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { + for (i = 0; i < aic->num_busses; i++) { s->busses[i].intr_ctrl = 0; s->busses[i].intr_status = 0; s->busses[i].cmd = 0; @@ -421,7 +422,7 @@ static void aspeed_i2c_reset(DeviceState *dev) } /* - * Address Definitions + * Address Definitions (AST2400 and AST2500) * * 0x000 ... 0x03F: Global Register * 0x040 ... 0x07F: Device 1 @@ -446,22 +447,24 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) int i; SysBusDevice *sbd = SYS_BUS_DEVICE(dev); AspeedI2CState *s = ASPEED_I2C(dev); + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, "aspeed.i2c", 0x1000); sysbus_init_mmio(sbd, &s->iomem); - for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { - char name[16]; - int offset = i < 7 ? 1 : 5; + for (i = 0; i < aic->num_busses; i++) { + char name[32]; + int offset = i < aic->gap ? 1 : 5; snprintf(name, sizeof(name), "aspeed.i2c.%d", i); s->busses[i].controller = s; s->busses[i].id = i; s->busses[i].bus = i2c_init_bus(dev, name); memory_region_init_io(&s->busses[i].mr, OBJECT(dev), - &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40); - memory_region_add_subregion(&s->iomem, 0x40 * (i + offset), + &aspeed_i2c_bus_ops, &s->busses[i], name, + aic->reg_size); + memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), &s->busses[i].mr); } } @@ -481,11 +484,51 @@ static const TypeInfo aspeed_i2c_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(AspeedI2CState), .class_init = aspeed_i2c_class_init, + .class_size = sizeof(AspeedI2CClass), + .abstract = true, +}; + +static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); + + dc->desc = "ASPEED 2400 I2C Controller"; + + aic->num_busses = 14; + aic->reg_size = 0x40; + aic->gap = 7; +} + +static const TypeInfo aspeed_2400_i2c_info = { + .name = TYPE_ASPEED_2400_I2C, + .parent = TYPE_ASPEED_I2C, + .class_init = aspeed_2400_i2c_class_init, +}; + +static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); + + dc->desc = "ASPEED 2500 I2C Controller"; + + aic->num_busses = 14; + aic->reg_size = 0x40; + aic->gap = 7; +} + +static const TypeInfo aspeed_2500_i2c_info = { + .name = TYPE_ASPEED_2500_I2C, + .parent = TYPE_ASPEED_I2C, + .class_init = aspeed_2500_i2c_class_init, }; static void aspeed_i2c_register_types(void) { type_register_static(&aspeed_i2c_info); + type_register_static(&aspeed_2400_i2c_info); + type_register_static(&aspeed_2500_i2c_info); } type_init(aspeed_i2c_register_types) @@ -494,9 +537,10 @@ type_init(aspeed_i2c_register_types) I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr) { AspeedI2CState *s = ASPEED_I2C(dev); + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); I2CBus *bus = NULL; - if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) { + if (busnr >= 0 && busnr < aic->num_busses) { bus = s->busses[busnr].bus; }