From patchwork Fri Oct 18 17:44:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176936 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1206754ill; Fri, 18 Oct 2019 11:10:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqyW7m8fRK7q8zLTqL/gC971j7WijbrHyP6tnWF/H2FFzhcxC2fM7NyI8jxkfeU8Fk9BQVJI X-Received: by 2002:aa7:c6d0:: with SMTP id b16mr11263688eds.108.1571422204497; Fri, 18 Oct 2019 11:10:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571422204; cv=none; d=google.com; s=arc-20160816; b=v87CzIMMRXQ8VRt3ATmej7SHdgsdwZBk0s9f3HmoG9vEtmC+MX1kttr/h0LL/g8Y6F RflQGfNxVQlV78FmT1HPbpAMfZ3XqdWIMqIlUjflXQCUTwCh7vjaALDXMQf7Jo8FwMp/ 2BAofCl07jOfki3bhwRYt+CAYjWrS4rxaS6R98js0/635GnRRrVIKbAorqeMaqkOUDSQ gPkuO0ZnwS5uBDdlLC1C2M37NIKsabT62fdcEZnCJqrGI8DNSZNy5TAwpEVn4yC44UIV QyB9UVkLgN82cOWPfHPAg2+KIGhKTq1OBO4vD9kVxh6oTAXlUCxmLVMCTq/YLC9e387h 9Fgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HNW+DKXClNFoWE5mAVnYOdmYoSifNB4F8oskeNBuM9U=; b=NEpDf3Tm956YReo80b7cR3XI7pcQRo9l9wKTaqU7NO7Tm2AMxdz3f+QNWgWb/GAFoF X9CwDbQnZEPJ52/l2hK26HhNyfZNwhRcUQbLA5R2KRaDm2FoJvpmflGgkTHzdEg0D6B2 e6H/l7mSrohWyPpwma5Fm+GBLy+5X4A+kOjvkc5XROl8sheaV1qtFk4zDO0W45Rm/Q/x 4YWz9ji0BOF8b9DLi8J3gE4+PB3rnBgGWUTY6e4/wmsbUJJ9fIlDilLDvEwur0x+ssEA bFzok7b7TihBkFJZxr9NEglrYp4Jk7Yw5Kf1/XUO/VtVFBbzEdqW/exk7OuLJ8O/f19Y X/0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X5gHWOT2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k9si3848243ejc.310.2019.10.18.11.10.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 Oct 2019 11:10:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X5gHWOT2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLWhP-0008Q5-Gk for patch@linaro.org; Fri, 18 Oct 2019 14:10:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59297) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLWIy-0006bk-IG for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLWIx-0005UM-CI for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:48 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:44718) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iLWIx-0005Td-6g for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:47 -0400 Received: by mail-pg1-x542.google.com with SMTP id e10so3741485pgd.11 for ; Fri, 18 Oct 2019 10:44:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HNW+DKXClNFoWE5mAVnYOdmYoSifNB4F8oskeNBuM9U=; b=X5gHWOT202VQRwzSmAviUtQdEEfz1DuVcXPtMUdkmFhvtmwVqWeZSSA6EuKgHx/ig7 IJPgcibeDPYPIfNviQe+aAwrVhmFYPXtVClBAy6yke4pVKHCBywOAzqCKLyLsEpbrRLZ aZ1pnVwGs1fMSLkP9yxe3rAjbIFEKeaTZy2bHj/6czbhpHCj1Eiqkqg2uwypAuII58jA sCWh9rBZiZc7XWufeR3G0fq4cG77JJk9ycnKofn2OVs/RVUzS6uXZeT0jd8NRS3MuJx/ kKki63c8PKpmdPc8fHfzVfpxdQh7LHh6MupU11Ba1Un3ltW5wkgFa3ZqZUldEH+SaQVi wC3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HNW+DKXClNFoWE5mAVnYOdmYoSifNB4F8oskeNBuM9U=; b=uM+MNuz9uAuSigx135mI2x/ftGePpiMmC7YEeW3kqhjBZfEZGt9Xe1mQvicavfgHHt xgm7kLGOOLgqfx8cYcFzikAHIq2OysCZTtfi55I9HZ2m/0PE/onIukD5ghQRVOoTmRq6 Yq78fmeRFsLvDWh6TmFQH1M8+xpieBq/P+Gl9qRKuq5QUf+BypQMrMrs2MjOKwr2a62v LhrX9+o5QPIknbN37dCHZ9wY2+AULPPclnr2G7Sv4+aw4nBySheuKyZjMubijgkO/bI6 YOHZ3Si15YrYwoJAtHOnzt6k/Dp8iYYthkn+eN9IrMFaGHcIlPlnHTfW8IMZgiYqEUtI /PEg== X-Gm-Message-State: APjAAAVs4he1nAA9jgjGSL4xRaqigDNDnkNalQF1FN26/a5/DHpk3ehN h180zqDBdhy6p8F4WMpWz3dTxGKz/54= X-Received: by 2002:a62:ae0d:: with SMTP id q13mr8199450pff.53.1571420685722; Fri, 18 Oct 2019 10:44:45 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 11/22] target/arm: Hoist computation of TBFLAG_A32.VFPEN Date: Fri, 18 Oct 2019 10:44:20 -0700 Message-Id: <20191018174431.1784-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are 3 conditions that each enable this flag. M-profile always enables; A-profile with EL1 as AA64 always enables. Both of these conditions can easily be cached. The final condition relies on the FPEXC register which we are not prepared to cache. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d961474ce..9909ff89d4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3192,7 +3192,7 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 398e5f5d6d..89aa6fd933 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11088,6 +11088,9 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, { uint32_t flags = 0; + /* v8M always enables the fpu. */ + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } @@ -11119,6 +11122,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { uint32_t flags = rebuild_hflags_aprofile(env); + + if (arm_el_is_aa64(env, 1)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } @@ -11250,14 +11257,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } pstate_for_ss = env->uncached_cpsr; }