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[209.51.188.17]) by mx.google.com with ESMTPS id i195si1386094qke.43.2019.12.11.09.12.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 11 Dec 2019 09:12:41 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o5jEuXbu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if5XU-0004Sp-Ms for patch@linaro.org; Wed, 11 Dec 2019 12:12:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39837) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1if5Qi-0005EQ-NM for qemu-devel@nongnu.org; Wed, 11 Dec 2019 12:05:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1if5Qg-0003Qr-S2 for qemu-devel@nongnu.org; Wed, 11 Dec 2019 12:05:40 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:34570) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1if5Qg-0003Om-F9 for qemu-devel@nongnu.org; Wed, 11 Dec 2019 12:05:38 -0500 Received: by mail-wm1-x344.google.com with SMTP id f4so1647778wmj.1 for ; Wed, 11 Dec 2019 09:05:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YQ48w0pDBwpVmbFzATtm4Ds62QLqzhKfE1NdsRw0nDA=; b=o5jEuXbughRSAbKskRVgAT2cK3x7GkHWwHz6982lWgAjGxfjgf5+d80c7VZR648J5H Yap9rBqX9jpl7lIljfBuycxaRVCXpSnuiYBB0ykgROotFuip1Hf0C+IkDKxIe9nQ9zOG ja8ar3p+29wZeJeO5i+TwsBbEl49zGQMAX30rxp5wqpfE4tbCgI+yMWCTxiF4HdDZNoU X+DJubi3RvzKYe8UAGzrbjEf9SEQP36UzoeJZF9eKQ38xtcS+smYtLjXNzeIyY0Ohq3h knp/HVJ14cbAKTUiWCLMcRjmI6zrB/Bwqm5P7yJTv8SSQ1DNO8zqp8pEFdf8BEdYCfa+ hp/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YQ48w0pDBwpVmbFzATtm4Ds62QLqzhKfE1NdsRw0nDA=; b=etrjjCaAfc1SAUcBOwPdztowoP0X/16SwbhvOGeG0CH/HKtct4FrURqIwOYTXXQ7tr IA/gQulJQDufx6JqaG6lWlRdt74nTpGLiijZdLv3w68Ihs1YpM2Kn8QbNBN9AygfSWSQ iUgsN1VJ1tNUs26FiL170ZJLyIJM63l5FN66ZtHQzl9O0bKdz2beuFMArUAey9ZRFeKz cR8KMTRoJTEw7Il4IZV0rYA7HJXmRBLyB3neIlTaew/qjla1PGYinijI/5pbXTq6trum T3fozMgqBd831X7oQWsAB4TWS9ag5RnzGndhWOg+7BHagOLFft+nM5Ke7DG1e6uaL7pl K7rQ== X-Gm-Message-State: APjAAAUt82f4Jap+kvjGGwoOAcSdgxcLwRSuCvR/kkyW4pTDK4Es74Xy PFRDSRQ9g32qceBal//zMX+odw== X-Received: by 2002:a1c:1d8c:: with SMTP id d134mr990808wmd.16.1576083937230; Wed, 11 Dec 2019 09:05:37 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id i8sm2971855wro.47.2019.12.11.09.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 09:05:30 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 92E6D1FF9A; Wed, 11 Dec 2019 17:05:23 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v3 11/20] target/arm: default SVE length to 64 bytes for linux-user Date: Wed, 11 Dec 2019 17:05:11 +0000 Message-Id: <20191211170520.7747-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: damien.hedde@greensocs.com, Peter Maydell , luis.machado@linaro.org, richard.henderson@linaro.org, "open list:ARM TCG CPUs" , alan.hayward@arm.com, =?utf-8?q?Alex?= =?utf-8?q?_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Linux kernel chooses the default of 64 bytes for SVE registers on the basis that it is the largest size on known hardware that won't grow the signal frame. We still honour the sve-max-vq property and userspace can expand the number of lanes by calling PR_SVE_SET_VL. This should not make any difference to SVE enabled software as the SVE is of course vector length agnostic. Signed-off-by: Alex Bennée --- v2 - tweak zcr_el[1] instead --- target/arm/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf..d42b88c9b73 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -199,9 +199,9 @@ static void arm_cpu_reset(CPUState *s) /* and to the SVE instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |= CPTR_EZ; - /* with maximum vector length */ + /* with reasonable vector length */ env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? - cpu->sve_max_vq - 1 : 0; + MIN(cpu->sve_max_vq - 1, 3) : 0; env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; /*