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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/13] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Date: Tue, 11 Feb 2020 17:37:19 +0000 Message-Id: <20200211173726.22541-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already define FIELD macros for ID_DFR0, so use them in the one place where we're doing direct bit value manipulation. Signed-off-by: Peter Maydell --- We have lots of this non-FIELD style in the code, of course; I change this one purely because it otherwise looks a bit odd sat next to the ID_AA64DFR0 line that was changed in the previous patch... --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dc582da8fa4..e7858b073b5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1603,7 +1603,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) #endif } else { cpu->id_aa64dfr0 = FIELD_DP32(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); - cpu->id_dfr0 &= ~(0xf << 24); + cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0); cpu->pmceid0 = 0; cpu->pmceid1 = 0; }