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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id d13sm12563559wrv.34.2020.04.12.15.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2020 15:37:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH-for-5.1 v3 22/24] hw/riscv/sifive_u: Store MemoryRegion in SiFiveUSoCState Date: Mon, 13 Apr 2020 00:36:17 +0200 Message-Id: <20200412223619.11284-23-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200412223619.11284-1-f4bug@amsat.org> References: <20200412223619.11284-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Sagar Karandikar , "Michael S. Tsirkin" , Jeff Cody , Jason Wang , Alistair Francis , "Edgar E. Iglesias" , Subbaraya Sundeep , qemu-block@nongnu.org, Markus Armbruster , Max Reitz , Joel Stanley , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Eduardo Habkost , Xie Changlong , Alistair Francis , Beniamino Galvani , qemu-arm@nongnu.org, Peter Chubb , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Palmer Dabbelt , David Gibson , Kevin Wolf , qemu-riscv@nongnu.org, Andrew Jeffery , Wen Congyang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , qemu-ppc@nongnu.org, Bastian Koppelmann , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Coccinelle reported: $ spatch ... --timeout 60 --sp-file \ scripts/coccinelle/simplify-init-realize-error_propagate.cocci HANDLING: ./hw/riscv/sifive_u.c >>> possible moves from riscv_sifive_u_soc_init() to riscv_sifive_u_soc_realize() in ./hw/riscv/sifive_u.c:473 While reviewing we notice storing the MemoryRegion in the device state, we'll be able to later automatically simplify the error propagation calls. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/riscv/sifive_u.h | 2 ++ hw/riscv/sifive_u.c | 10 ++++------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 82667b5746..254c6a64f8 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState { SiFiveUPRCIState prci; SiFiveUOTPState otp; CadenceGEMState gem; + MemoryRegion mask_rom; + MemoryRegion l2lim_mem; } SiFiveUSoCState; #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 754af19eef..96177c1977 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -478,8 +478,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) SiFiveUSoCState *s = RISCV_U_SOC(dev); const struct MemmapEntry *memmap = sifive_u_memmap; MemoryRegion *system_memory = get_system_memory(); - MemoryRegion *mask_rom = g_new(MemoryRegion, 1); - MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; char *plic_hart_config; size_t plic_hart_config_len; @@ -503,10 +501,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) &error_abort); /* boot rom */ - memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", + memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", memmap[SIFIVE_U_MROM].size, &error_fatal); memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, - mask_rom); + &s->mask_rom); /* * Add L2-LIM at reset size. @@ -517,10 +515,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) * leave it enabled all the time. This won't break anything, but will be * too generous to misbehaving guests. */ - memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", + memory_region_init_ram(&s->l2lim_mem, NULL, "riscv.sifive.u.l2lim", memmap[SIFIVE_U_L2LIM].size, &error_fatal); memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, - l2lim_mem); + &s->l2lim_mem); /* create PLIC hart topology configuration string */ plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *