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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id f63sm12083825wma.47.2020.04.12.15.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2020 15:42:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH-for-5.1 v3 07/23] hw/riscv/sifive: Add missing error-propagation code Date: Mon, 13 Apr 2020 00:41:28 +0200 Message-Id: <20200412224144.12205-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200412224144.12205-1-f4bug@amsat.org> References: <20200412224144.12205-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Sagar Karandikar , "Michael S. Tsirkin" , Jason Wang , Mark Cave-Ayland , Alistair Francis , "Edgar E. Iglesias" , Subbaraya Sundeep , qemu-block@nongnu.org, Markus Armbruster , Aleksandar Markovic , Max Reitz , Joel Stanley , Palmer Dabbelt , Aleksandar Rikalo , David Gibson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Eduardo Habkost , Alistair Francis , Beniamino Galvani , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , Richard Henderson , Kevin Wolf , qemu-riscv@nongnu.org, Andrew Jeffery , Bastian Koppelmann , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Andrew Baumann , Jean-Christophe Dubois , Michael Walle , qemu-ppc@nongnu.org, Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Patch created mechanically by running: $ spatch \ --macro-file scripts/cocci-macro-file.h --include-headers \ --sp-file scripts/coccinelle/use-error_propagate-in-realize.cocci \ --keep-comments --smpl-spacing --in-place --dir hw Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/sifive_e.c | 6 +++++- hw/riscv/sifive_u.c | 24 ++++++++++++++++++++---- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0be8b52147..6d4e141ff7 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -156,7 +156,11 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) MemoryRegion *sys_mem = get_system_memory(); object_property_set_bool(OBJECT(&s->cpus), true, "realized", - &error_abort); + &err); + if (err) { + error_propagate(errp, err); + return; + } /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index e13ab34de4..b07526aba1 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -508,9 +508,17 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) NICInfo *nd = &nd_table[0]; object_property_set_bool(OBJECT(&s->e_cpus), true, "realized", - &error_abort); + &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->u_cpus), true, "realized", - &error_abort); + &err); + if (err) { + error_propagate(errp, err); + return; + } /* * The cluster must be realized after the RISC-V hart array container, * as the container's CPU object is only created on realize, and the @@ -518,9 +526,17 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) * cluster is realized. */ object_property_set_bool(OBJECT(&s->e_cluster), true, "realized", - &error_abort); + &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", - &error_abort); + &err); + if (err) { + error_propagate(errp, err); + return; + } /* create PLIC hart topology configuration string */ plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *