diff mbox series

[v2,24/36] tcg/i386: Use tcg_constant_vec with tcg vec expanders

Message ID 20200422011722.13287-25-richard.henderson@linaro.org
State Superseded
Headers show
Series tcg 5.1 omnibus patch set | expand

Commit Message

Richard Henderson April 22, 2020, 1:17 a.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tcg/i386/tcg-target.inc.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

-- 
2.20.1

Comments

Alex Bennée April 22, 2020, 7:43 p.m. UTC | #1 
Richard Henderson <richard.henderson@linaro.org> writes:

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  tcg/i386/tcg-target.inc.c | 26 +++++++++++++-------------

>  1 file changed, 13 insertions(+), 13 deletions(-)

>

> diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c

> index 9cb627d6eb..deace219d2 100644

> --- a/tcg/i386/tcg-target.inc.c

> +++ b/tcg/i386/tcg-target.inc.c

> @@ -3452,7 +3452,7 @@ static void expand_vec_sari(TCGType type, unsigned vece,

>  static void expand_vec_mul(TCGType type, unsigned vece,

>                             TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)

>  {

> -    TCGv_vec t1, t2, t3, t4;

> +    TCGv_vec t1, t2, t3, t4, zero;

>  

>      tcg_debug_assert(vece == MO_8);

>  

> @@ -3470,11 +3470,11 @@ static void expand_vec_mul(TCGType type, unsigned vece,

>      case TCG_TYPE_V64:

>          t1 = tcg_temp_new_vec(TCG_TYPE_V128);

>          t2 = tcg_temp_new_vec(TCG_TYPE_V128);

> -        tcg_gen_dup16i_vec(t2, 0);

> +        zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0);

>          vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,

> -                  tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));

> +                  tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero));

>          vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,

> -                  tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));

> +                  tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2));

>          tcg_gen_mul_vec(MO_16, t1, t1, t2);

>          tcg_gen_shri_vec(MO_16, t1, t1, 8);

>          vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,

> @@ -3489,15 +3489,15 @@ static void expand_vec_mul(TCGType type, unsigned vece,

>          t2 = tcg_temp_new_vec(type);

>          t3 = tcg_temp_new_vec(type);

>          t4 = tcg_temp_new_vec(type);

> -        tcg_gen_dup16i_vec(t4, 0);

> +        zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0);

>          vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,

> -                  tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4));

> +                  tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero));

>          vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,

> -                  tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2));

> +                  tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2));

>          vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,

> -                  tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));

> +                  tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero));

>          vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,

> -                  tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));

> +                  tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2));

>          tcg_gen_mul_vec(MO_16, t1, t1, t2);

>          tcg_gen_mul_vec(MO_16, t3, t3, t4);

>          tcg_gen_shri_vec(MO_16, t1, t1, 8);

> @@ -3525,7 +3525,7 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,

>          NEED_UMIN = 8,

>          NEED_UMAX = 16,

>      };

> -    TCGv_vec t1, t2;

> +    TCGv_vec t1, t2, t3;

>      uint8_t fixup;

>  

>      switch (cond) {

> @@ -3596,9 +3596,9 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,

>      } else if (fixup & NEED_BIAS) {

>          t1 = tcg_temp_new_vec(type);

>          t2 = tcg_temp_new_vec(type);

> -        tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));

> -        tcg_gen_sub_vec(vece, t1, v1, t2);

> -        tcg_gen_sub_vec(vece, t2, v2, t2);

> +        t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1));

> +        tcg_gen_sub_vec(vece, t1, v1, t3);

> +        tcg_gen_sub_vec(vece, t2, v2, t3);

>          v1 = t1;

>          v2 = t2;

>          cond = tcg_signed_cond(cond);



-- 
Alex Bennée
diff mbox series

Patch

diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 9cb627d6eb..deace219d2 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -3452,7 +3452,7 @@  static void expand_vec_sari(TCGType type, unsigned vece,
 static void expand_vec_mul(TCGType type, unsigned vece,
                            TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
 {
-    TCGv_vec t1, t2, t3, t4;
+    TCGv_vec t1, t2, t3, t4, zero;
 
     tcg_debug_assert(vece == MO_8);
 
@@ -3470,11 +3470,11 @@  static void expand_vec_mul(TCGType type, unsigned vece,
     case TCG_TYPE_V64:
         t1 = tcg_temp_new_vec(TCG_TYPE_V128);
         t2 = tcg_temp_new_vec(TCG_TYPE_V128);
-        tcg_gen_dup16i_vec(t2, 0);
+        zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0);
         vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
-                  tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+                  tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero));
         vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
-                  tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));
+                  tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2));
         tcg_gen_mul_vec(MO_16, t1, t1, t2);
         tcg_gen_shri_vec(MO_16, t1, t1, 8);
         vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
@@ -3489,15 +3489,15 @@  static void expand_vec_mul(TCGType type, unsigned vece,
         t2 = tcg_temp_new_vec(type);
         t3 = tcg_temp_new_vec(type);
         t4 = tcg_temp_new_vec(type);
-        tcg_gen_dup16i_vec(t4, 0);
+        zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0);
         vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
-                  tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
+                  tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero));
         vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
-                  tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
+                  tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2));
         vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
-                  tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
+                  tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero));
         vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
-                  tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
+                  tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2));
         tcg_gen_mul_vec(MO_16, t1, t1, t2);
         tcg_gen_mul_vec(MO_16, t3, t3, t4);
         tcg_gen_shri_vec(MO_16, t1, t1, 8);
@@ -3525,7 +3525,7 @@  static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
         NEED_UMIN = 8,
         NEED_UMAX = 16,
     };
-    TCGv_vec t1, t2;
+    TCGv_vec t1, t2, t3;
     uint8_t fixup;
 
     switch (cond) {
@@ -3596,9 +3596,9 @@  static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
     } else if (fixup & NEED_BIAS) {
         t1 = tcg_temp_new_vec(type);
         t2 = tcg_temp_new_vec(type);
-        tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));
-        tcg_gen_sub_vec(vece, t1, v1, t2);
-        tcg_gen_sub_vec(vece, t2, v2, t2);
+        t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1));
+        tcg_gen_sub_vec(vece, t1, v1, t3);
+        tcg_gen_sub_vec(vece, t2, v2, t3);
         v1 = t1;
         v2 = t2;
         cond = tcg_signed_cond(cond);