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Thu, 18 Jun 2020 00:11:34 +0000 (GMT) Received: from pompom.ibm.com (unknown [9.65.216.12]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 18 Jun 2020 00:11:33 +0000 (GMT) From: Lijun Pan To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 7/7] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Date: Wed, 17 Jun 2020 19:11:27 -0500 Message-Id: <20200618001127.34438-8-ljp@linux.ibm.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200618001127.34438-1-ljp@linux.ibm.com> References: <20200618001127.34438-1-ljp@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-06-17_12:2020-06-17, 2020-06-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=999 suspectscore=2 adultscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2006170180 Received-SPF: pass client-ip=148.163.156.1; envelope-from=ljp@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/17 20:11:31 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lijun Pan Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" vdivsw: Vector Divide Signed Word vdivuw: Vector Divide Unsigned Word vdivsd: Vector Divide Signed Doubleword vdivud: Vector Divide Unsigned Doubleword vmodsw: Vector Modulo Signed Word vmoduw: Vector Modulo Unsigned Word vmodsd: Vector Modulo Signed Doubleword vmodud: Vector Modulo Unsigned Doubleword Signed-off-by: Lijun Pan --- v2: fix coding style use Power ISA 3.1 flag target/ppc/helper.h | 8 ++++++++ target/ppc/int_helper.c | 19 +++++++++++++++++++ target/ppc/translate.c | 3 +++ target/ppc/translate/vmx-impl.inc.c | 15 +++++++++++++++ target/ppc/translate/vmx-ops.inc.c | 17 +++++++++++++++-- 5 files changed, 60 insertions(+), 2 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 1aed2087cf..823999a8c2 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -190,6 +190,14 @@ DEF_HELPER_3(vmulhsw, void, avr, avr, avr) DEF_HELPER_3(vmulhuw, void, avr, avr, avr) DEF_HELPER_3(vmulhsd, void, avr, avr, avr) DEF_HELPER_3(vmulhud, void, avr, avr, avr) +DEF_HELPER_3(vdivsw, void, avr, avr, avr) +DEF_HELPER_3(vdivuw, void, avr, avr, avr) +DEF_HELPER_3(vdivsd, void, avr, avr, avr) +DEF_HELPER_3(vdivud, void, avr, avr, avr) +DEF_HELPER_3(vmodsw, void, avr, avr, avr) +DEF_HELPER_3(vmoduw, void, avr, avr, avr) +DEF_HELPER_3(vmodsd, void, avr, avr, avr) +DEF_HELPER_3(vmodud, void, avr, avr, avr) DEF_HELPER_3(vslo, void, avr, avr, avr) DEF_HELPER_3(vsro, void, avr, avr, avr) DEF_HELPER_3(vsrv, void, avr, avr, avr) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 9a0937810f..bc3640166d 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -575,6 +575,25 @@ VARITH_DO(mulld, *, s64) #undef VARITH_DO #undef VARITH +#define VDIV_MOD_DO(name, op, element) \ + void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + { \ + int i; \ + \ + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ + r->element[i] = a->element[i] op b->element[i]; \ + } \ + } +VDIV_MOD_DO(divsw, /, s32) +VDIV_MOD_DO(divuw, /, u32) +VDIV_MOD_DO(divsd, /, s64) +VDIV_MOD_DO(divud, /, u64) +VDIV_MOD_DO(modsw, %, s32) +VDIV_MOD_DO(moduw, %, u32) +VDIV_MOD_DO(modsd, %, s64) +VDIV_MOD_DO(modud, %, u64) +#undef VDIV_MOD_DO + #define VARITHFP(suffix, func) \ void helper_v##suffix(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, \ ppc_avr_t *b) \ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d686e6084a..6d5af650e4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -388,6 +388,9 @@ GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) +#define GEN_HANDLER_BOTH(name, opc1, opc2, opc3, inval0, inval1, type0, type1) \ +GEN_OPCODE_DUAL(name, opc1, opc2, opc3, inval0, inval1, type0, type1) + typedef struct opcode_t { unsigned char opc1, opc2, opc3, opc4; #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index c494a7aebb..e0b8658d1f 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -798,6 +798,9 @@ static void trans_vclzd(DisasContext *ctx) tcg_temp_free_i64(avr); } +static void gen_vexptefp(DisasContext *ctx); +static void gen_vlogefp(DisasContext *ctx); + GEN_VXFORM(vmuloub, 4, 0); GEN_VXFORM(vmulouh, 4, 1); GEN_VXFORM(vmulouw, 4, 2); @@ -822,6 +825,18 @@ GEN_VXFORM(vmulhsw, 4, 14); GEN_VXFORM_DUAL(vmulesw, PPC_ALTIVEC, PPC_NONE, vmulhsw, PPC_NONE, PPC2_ISA310); GEN_VXFORM(vmulhsd, 4, 15); +GEN_VXFORM(vdivuw, 5, 2); +GEN_VXFORM(vdivud, 5, 3); +GEN_VXFORM(vdivsw, 5, 6); +GEN_VXFORM_DUAL_EXT(vexptefp, PPC_ALTIVEC, PPC_NONE, 0x001f0000, + vdivsw, PPC_NONE, PPC2_ISA310, 0x00000000); +GEN_VXFORM(vdivsd, 5, 7); +GEN_VXFORM_DUAL_EXT(vlogefp, PPC_ALTIVEC, PPC_NONE, 0x001f0000, + vdivsd, PPC_NONE, PPC2_ISA310, 0x00000000); +GEN_VXFORM(vmoduw, 5, 26); +GEN_VXFORM(vmodud, 5, 27); +GEN_VXFORM(vmodsw, 5, 30); +GEN_VXFORM(vmodsd, 5, 31); GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4); GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5); GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6); diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c index f3f4855111..528458cb25 100644 --- a/target/ppc/translate/vmx-ops.inc.c +++ b/target/ppc/translate/vmx-ops.inc.c @@ -54,6 +54,11 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310) #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) +#define GEN_VXFORM_DUAL_BOTH(name0, name1, opc2, opc3, inval0, \ + inval1, type0, type1) \ +GEN_HANDLER_BOTH(name0##_##name1, 0x4, opc2, opc3, inval0, \ + inval1, type0, type1) + #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1), @@ -116,6 +121,16 @@ GEN_VXFORM(vmulesb, 4, 12), GEN_VXFORM(vmulesh, 4, 13), GEN_VXFORM_DUAL(vmulesw, vmulhsw, 4, 14, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_310(vmulhsd, 4, 15), +GEN_VXFORM_310(vdivuw, 5, 2), +GEN_VXFORM_310(vdivud, 5, 3), +GEN_VXFORM_DUAL_BOTH(vexptefp, vdivsw, 5, 6, 0x001f0000, 0x00000000, + PPC_ALTIVEC, PPC2_ISA310), +GEN_VXFORM_DUAL_BOTH(vlogefp, vdivsd, 5, 7, 0x001f0000, 0x00000000, + PPC_ALTIVEC, PPC2_ISA310), +GEN_VXFORM_310(vmoduw, 5, 26), +GEN_VXFORM_310(vmodud, 5, 27), +GEN_VXFORM_310(vmodsw, 5, 30), +GEN_VXFORM_310(vmodsd, 5, 31), GEN_VXFORM(vslb, 2, 4), GEN_VXFORM(vslh, 2, 5), GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE), @@ -259,8 +274,6 @@ GEN_VXFORM_NOA(vupkhpx, 7, 13), GEN_VXFORM_NOA(vupklpx, 7, 15), GEN_VXFORM_NOA(vrefp, 5, 4), GEN_VXFORM_NOA(vrsqrtefp, 5, 5), -GEN_VXFORM_NOA(vexptefp, 5, 6), -GEN_VXFORM_NOA(vlogefp, 5, 7), GEN_VXFORM_NOA(vrfim, 5, 11), GEN_VXFORM_NOA(vrfin, 5, 8), GEN_VXFORM_NOA(vrfip, 5, 10),