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[73.47.162.176]) by smtp.gmail.com with ESMTPSA id v11sm9733646pgs.22.2020.07.31.05.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2020 05:51:43 -0700 (PDT) From: Robert Foley To: qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/core: Add bql_interrupt flag to CPUClass Date: Fri, 31 Jul 2020 08:51:26 -0400 Message-Id: <20200731125127.30866-2-robert.foley@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200731125127.30866-1-robert.foley@linaro.org> References: <20200731125127.30866-1-robert.foley@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=robert.foley@linaro.org; helo=mail-pl1-x634.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.foley@linaro.org, Eduardo Habkost , cota@braap.org, pbonzini@redhat.com, peter.puhov@linaro.org, alex.bennee@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The new flag bql_interrupt, allows the CPUClass to determine if the BQL should be held during calls to cpu_exec_interrupt or do_interrupt. This is being added in preparation for changes in cpu_handle_interrupt, which will use this flag. Signed-off-by: Robert Foley --- hw/core/cpu.c | 1 + include/hw/core/cpu.h | 8 ++++++++ 2 files changed, 9 insertions(+) -- 2.17.1 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 8707ce2c34..7ab88caa97 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -425,6 +425,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->cpu_exec_exit = cpu_common_noop; k->cpu_exec_interrupt = cpu_common_exec_interrupt; k->adjust_watchpoint_address = cpu_adjust_watchpoint_address; + k->bql_interrupt = true; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize = cpu_common_realizefn; dc->unrealize = cpu_common_unrealizefn; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6a2c77682f..d2c426ee5d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -157,6 +157,8 @@ struct TranslationBlock; * @disas_set_info: Setup architecture specific components of disassembly info * @adjust_watchpoint_address: Perform a target-specific adjustment to an * address before attempting to match it against watchpoints. + * @bql_interrupt: Hold BQL while performing the cpu_exec_interrupt + * or do_interrupt call. * * Represents a CPU family or model. */ @@ -227,6 +229,7 @@ typedef struct CPUClass { /* Keep non-pointer data at the end to minimize holes. */ int gdb_num_core_regs; bool gdb_stop_before_watchpoint; + bool bql_interrupt; } CPUClass; /* @@ -589,6 +592,11 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) } } +static inline void cpu_class_enable_bql_interrupt(CPUClass *cc) +{ + cc->bql_interrupt = true; +} + /** * qemu_tcg_mttcg_enabled: * Check whether we are running MultiThread TCG or not.