From patchwork Fri Sep 18 18:37:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 305004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2582C43463 for ; Fri, 18 Sep 2020 19:34:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A29A21734 for ; Fri, 18 Sep 2020 19:34:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AECXOMj6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A29A21734 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:58444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kJM8u-0000xu-1x for qemu-devel@archiver.kernel.org; Fri, 18 Sep 2020 15:34:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kJLHk-0000nA-K3 for qemu-devel@nongnu.org; Fri, 18 Sep 2020 14:39:05 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:41131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kJLHd-0007CW-OM for qemu-devel@nongnu.org; Fri, 18 Sep 2020 14:39:04 -0400 Received: by mail-pf1-x434.google.com with SMTP id z19so3986295pfn.8 for ; Fri, 18 Sep 2020 11:38:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aEKi5HB5DZ4Vz/ADDH+O3l8Z8WFjuqPobP8PDP6SNRs=; b=AECXOMj6GxW9kYWw6LBi2ll54mYHkrx1QWyYG55UsfqTqtcyKYaaPKnobYbWxNf6M+ FzINm1r+5Qc+vKZatD/kOOQWilEeB0UjL1A4uW9QnvF76AsQj/Uc3zXzkgJNlfHlKpTo tz8PU0Wj0OwqupkvQlLta1Pd/zPBFj7fN/nu8ANSkNfTDe/i+FbLWSte5mIjRO4dOcZd Z6QufyfbbR2W0NiaLYePSGZ3MXL/1CuylkFBIX9maOTrgfoMAzCf16bd4fapM1Ay/txc e7JNMCGo613P5pVXCxaTjox4Yep6ps5ejxxZijIi3svveU+z3NJq9iH289u8xsKFskb4 L5Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aEKi5HB5DZ4Vz/ADDH+O3l8Z8WFjuqPobP8PDP6SNRs=; b=FRHrdNm6MQtV9cT1gnkslqw3yKejUMgePnbYyc7HJVuRtJr6X3et9TjU2dOWMLCQCh UZx0ceR0U63UtAoC35llfv6HFxBDNVlS7xmP7CJQ9irveAgOE23dAoVU6RwRGbMY5heg z7eQDE3lJCWqQVyHlp53MkeZlEBJY1KhVQxGvQkYWI+EfJbf4zkltbdVbyzFcUkmrk7U JWwBQexl5WOGhpCA899CSTf+7GvuDBNR/H4BINmAEpuQdnQYeKhdnC7JSMXfeanubSVS eo9RnfPyFG6XEJU8K7OgRQi99QWLlKwPSTq3x1EhjHCFM4SCGAYknM+eYmVB3xzf01JG z7Tw== X-Gm-Message-State: AOAM530BfUMFjzNpRyMMaEBrWL2u2KGLvcIkJakbJc6sTPS/DN/8pKs7 5jADfcAtlNRlKZnuQZyFqZOnZo5HQM0jlw== X-Google-Smtp-Source: ABdhPJyEpd/jrYOLeo5vUxNc6FjJek6NGfwZZMz4tXUeGbAy2KzlDJXxYVKAO8Ui5jYVZG+HTl3HuA== X-Received: by 2002:a63:e708:: with SMTP id b8mr408090pgi.77.1600454336044; Fri, 18 Sep 2020 11:38:56 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id f4sm3680723pfj.147.2020.09.18.11.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2020 11:38:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 48/81] target/arm: Implement SVE2 gather load insns Date: Fri, 18 Sep 2020 11:37:18 -0700 Message-Id: <20200918183751.2787647-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200918183751.2787647-1-richard.henderson@linaro.org> References: <20200918183751.2787647-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Stephen Long Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1W (vector plus scalar) Signed-off-by: Stephen Long Message-Id: <20200422152343.12493-1-steplong@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/sve.decode | 11 +++++++++++ target/arm/translate-sve.c | 8 ++++++++ 2 files changed, 19 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index dc784dcabe..1b5bd2d193 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1389,6 +1389,17 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx +### SVE2 Memory Gather Load Group + +# SVE2 64-bit gather non-temporal load +# (scalar plus unpacked 32-bit unscaled offsets) +LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ + &rprr_gather_load xs=0 esz=3 scale=0 ff=0 + +# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) +LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ + &rprr_gather_load xs=0 esz=2 scale=0 ff=0 + ### SVE2 Memory Store Group # SVE2 64-bit scatter non-temporal store (vector plus scalar) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index af8feff707..0cb10ac3e2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6020,6 +6020,14 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) return true; } +static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) +{ + if (!dc_isar_feature(aa64_sve2, s)) { + return false; + } + return trans_LD1_zprz(s, a); +} + /* Indexed by [mte][be][xs][msz]. */ static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][2][3] = { { /* MTE Inactive */