| Message ID | 20200921034729.432931-2-f4bug@amsat.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2 | expand |
On 9/21/20 5:47 AM, Philippe Mathieu-Daudé wrote: > The Raspberry firmware is closed-source. While running it, it > accesses various I/O registers. Logging these accesses as UNIMP > (unimplemented) help to understand what the firmware is doing > (ideally we want it able to boot a Linux kernel). > > Document various blocks we might use later. > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> > --- > include/hw/arm/raspi_platform.h | 51 +++++++++++++++++++++++++++------ > 1 file changed, 43 insertions(+), 8 deletions(-) > > diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h > index 61b04a1bd4a..c7f50b260f6 100644 > --- a/include/hw/arm/raspi_platform.h > +++ b/include/hw/arm/raspi_platform.h > @@ -20,20 +20,29 @@ > * You should have received a copy of the GNU General Public License > * along with this program; if not, write to the Free Software > * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + * > + * Various undocumented addresses and names come from Herman Hermitage's VC4 > + * documentation: > + * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map > */ > > #ifndef HW_ARM_RASPI_PLATFORM_H > #define HW_ARM_RASPI_PLATFORM_H > > #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ > -#define IC0_OFFSET 0x2000 > +#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */ > +#define INTE_OFFSET 0x2000 /* VC Interrupt controller */ > #define ST_OFFSET 0x3000 /* System Timer */ > +#define TXP_OFFSET 0x4000 /* Transposer */ > +#define JPEG_OFFSET 0x5000 > #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ > #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ > -#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */ > +#define ARBA_OFFSET 0x9000 > +#define BRDG_OFFSET 0xa000 > +#define ARM_OFFSET 0xB000 /* ARM control block */ > #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) > #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ > -#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ > +#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */ > #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores > * Doorbells & Mailboxes */ > #define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ > @@ -42,24 +51,50 @@ > #define AVS_OFFSET 0x103000 /* Audio Video Standard */ > #define RNG_OFFSET 0x104000 > #define GPIO_OFFSET 0x200000 > -#define UART0_OFFSET 0x201000 > -#define MMCI0_OFFSET 0x202000 > -#define I2S_OFFSET 0x203000 > -#define SPI0_OFFSET 0x204000 > +#define UART0_OFFSET 0x201000 /* PL011 */ > +#define MMCI0_OFFSET 0x202000 /* Legacy MMC */ > +#define I2S_OFFSET 0x203000 /* PCM */ > +#define SPI0_OFFSET 0x204000 /* SPI master */ > #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ > +#define PIXV0_OFFSET 0x206000 > +#define PIXV1_OFFSET 0x207000 > +#define DPI_OFFSET 0x208000 > +#define DSI0_OFFSET 0x209000 /* Display Serial Interface */ > +#define PWM_OFFSET 0x20c000 > +#define PERM_OFFSET 0x20d000 > +#define TEC_OFFSET 0x20e000 > #define OTP_OFFSET 0x20f000 > +#define SLIM_OFFSET 0x210000 /* SLIMbus */ > +#define CPG_OFFSET 0x211000 > #define THERMAL_OFFSET 0x212000 > -#define BSC_SL_OFFSET 0x214000 /* SPI slave */ > +#define AVSP_OFFSET 0x213000 > +#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */ > #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ > #define EMMC1_OFFSET 0x300000 > +#define EMMC2_OFFSET 0x340000 > +#define HVS_OFFSET 0x400000 > #define SMI_OFFSET 0x600000 > +#define DSI1_OFFSET 0x700000 > +#define UCAM_OFFSET 0x800000 > +#define CMI_OFFSET 0x802000 > #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ > #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ > +#define VECA_OFFSET 0x806000 > +#define PIXV2_OFFSET 0x807000 > +#define HDMI_OFFSET 0x808000 > +#define HDCP_OFFSET 0x809000 > +#define ARBR0_OFFSET 0x80a000 > #define DBUS_OFFSET 0x900000 > #define AVE0_OFFSET 0x910000 > #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ > +#define V3D_OFFSET 0xc00000 > #define SDRAMC_OFFSET 0xe00000 > +#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */ > +#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */ > +#define ARBR1_OFFSET 0xe04000 > #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ > +#define DCRC_OFFSET 0xe07000 > +#define AXIP_OFFSET 0xe08000 > > /* GPU interrupts */ > #define INTERRUPT_TIMER0 0 >
diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h index 61b04a1bd4a..c7f50b260f6 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -20,20 +20,29 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Various undocumented addresses and names come from Herman Hermitage's VC4 + * documentation: + * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map */ #ifndef HW_ARM_RASPI_PLATFORM_H #define HW_ARM_RASPI_PLATFORM_H #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ -#define IC0_OFFSET 0x2000 +#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */ +#define INTE_OFFSET 0x2000 /* VC Interrupt controller */ #define ST_OFFSET 0x3000 /* System Timer */ +#define TXP_OFFSET 0x4000 /* Transposer */ +#define JPEG_OFFSET 0x5000 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ -#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */ +#define ARBA_OFFSET 0x9000 +#define BRDG_OFFSET 0xa000 +#define ARM_OFFSET 0xB000 /* ARM control block */ #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ -#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ +#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */ #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores * Doorbells & Mailboxes */ #define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ @@ -42,24 +51,50 @@ #define AVS_OFFSET 0x103000 /* Audio Video Standard */ #define RNG_OFFSET 0x104000 #define GPIO_OFFSET 0x200000 -#define UART0_OFFSET 0x201000 -#define MMCI0_OFFSET 0x202000 -#define I2S_OFFSET 0x203000 -#define SPI0_OFFSET 0x204000 +#define UART0_OFFSET 0x201000 /* PL011 */ +#define MMCI0_OFFSET 0x202000 /* Legacy MMC */ +#define I2S_OFFSET 0x203000 /* PCM */ +#define SPI0_OFFSET 0x204000 /* SPI master */ #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ +#define PIXV0_OFFSET 0x206000 +#define PIXV1_OFFSET 0x207000 +#define DPI_OFFSET 0x208000 +#define DSI0_OFFSET 0x209000 /* Display Serial Interface */ +#define PWM_OFFSET 0x20c000 +#define PERM_OFFSET 0x20d000 +#define TEC_OFFSET 0x20e000 #define OTP_OFFSET 0x20f000 +#define SLIM_OFFSET 0x210000 /* SLIMbus */ +#define CPG_OFFSET 0x211000 #define THERMAL_OFFSET 0x212000 -#define BSC_SL_OFFSET 0x214000 /* SPI slave */ +#define AVSP_OFFSET 0x213000 +#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */ #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ #define EMMC1_OFFSET 0x300000 +#define EMMC2_OFFSET 0x340000 +#define HVS_OFFSET 0x400000 #define SMI_OFFSET 0x600000 +#define DSI1_OFFSET 0x700000 +#define UCAM_OFFSET 0x800000 +#define CMI_OFFSET 0x802000 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ +#define VECA_OFFSET 0x806000 +#define PIXV2_OFFSET 0x807000 +#define HDMI_OFFSET 0x808000 +#define HDCP_OFFSET 0x809000 +#define ARBR0_OFFSET 0x80a000 #define DBUS_OFFSET 0x900000 #define AVE0_OFFSET 0x910000 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ +#define V3D_OFFSET 0xc00000 #define SDRAMC_OFFSET 0xe00000 +#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */ +#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */ +#define ARBR1_OFFSET 0xe04000 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ +#define DCRC_OFFSET 0xe07000 +#define AXIP_OFFSET 0xe08000 /* GPU interrupts */ #define INTERRUPT_TIMER0 0