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[83.53.161.74]) by smtp.gmail.com with ESMTPSA id 11sm4822708wmi.14.2020.09.27.02.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Sep 2020 02:19:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH] ssi: Display chip select polarity in monitor 'info qtree' Date: Sun, 27 Sep 2020 11:19:46 +0200 Message-Id: <20200927091946.65491-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , Alistair Francis , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" It is sometime useful to verify a device chip select polarity on a SPI bus. Since we have this information available, display it in the 'info qtree' monitor output: $ qemu-system-arm -M lm3s6965evb -monitor stdio -S (qemu) info qtree [...] dev: pl022, id "" gpio-out "sysbus-irq" 1 mmio 0000000040008000/0000000000001000 bus: ssi type SSI dev: ssd0323, id "" gpio-in "" 1 gpio-in "ssi-gpio-cs" 1 chip select polarity: high <--- dev: ssi-sd, id "" gpio-in "ssi-gpio-cs" 1 chip select polarity: low <--- bus: sd-bus type sd-bus dev: sd-card, id "" spec_version = 2 (0x2) drive = "sd0" spi = true Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater --- hw/ssi/ssi.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c index 4278d0e4440..4c9f8d66d23 100644 --- a/hw/ssi/ssi.c +++ b/hw/ssi/ssi.c @@ -17,6 +17,7 @@ #include "migration/vmstate.h" #include "qemu/module.h" #include "qapi/error.h" +#include "monitor/monitor.h" #include "qom/object.h" struct SSIBus { @@ -26,10 +27,31 @@ struct SSIBus { #define TYPE_SSI_BUS "SSI" OBJECT_DECLARE_SIMPLE_TYPE(SSIBus, SSI_BUS) +static void ssi_print_dev(Monitor *mon, DeviceState *dev, int indent) +{ + static const char *const polarity_s[] = { + [SSI_CS_NONE] = "unknown", + [SSI_CS_LOW] = "low", + [SSI_CS_HIGH] = "high" + }; + SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(dev); + + monitor_printf(mon, "%*schip select polarity: %s\n", + indent, "", polarity_s[ssc->cs_polarity]); +} + +static void ssi_bus_class_init(ObjectClass *klass, void *data) +{ + BusClass *k = BUS_CLASS(klass); + + k->print_dev = ssi_print_dev; +} + static const TypeInfo ssi_bus_info = { .name = TYPE_SSI_BUS, .parent = TYPE_BUS, .instance_size = sizeof(SSIBus), + .class_init = ssi_bus_class_init, }; static void ssi_cs_default(void *opaque, int n, int level)