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Mon, 5 Oct 2020 20:52:35 +0000 (UTC) Received: from localhost (ovpn-119-102.rdu2.redhat.com [10.10.119.102]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2925618E3C; Mon, 5 Oct 2020 20:52:35 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Subject: [PATCH 2/3] docs/devel/qtest: Include protocol spec in document Date: Mon, 5 Oct 2020 16:52:27 -0400 Message-Id: <20201005205228.697463-3-ehabkost@redhat.com> In-Reply-To: <20201005205228.697463-1-ehabkost@redhat.com> References: <20201005205228.697463-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ehabkost@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=ehabkost@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/05 02:11:31 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.733, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Include the QTest Protocol doc string in docs/devel/qtest.rst, after converting it to use Sphinx syntax. Signed-off-by: Eduardo Habkost --- docs/devel/qtest.rst | 12 ++++++-- softmmu/qtest.c | 73 +++++++++++++++++++++++++++++++++++++++----- 2 files changed, 75 insertions(+), 10 deletions(-) diff --git a/docs/devel/qtest.rst b/docs/devel/qtest.rst index 86dec84a0ba..3bf9ebee7f0 100644 --- a/docs/devel/qtest.rst +++ b/docs/devel/qtest.rst @@ -4,8 +4,8 @@ QTest Device Emulation Testing Framework QTest is a device emulation testing framework. It can be very useful to test device models; it could also control certain aspects of QEMU (such as virtual -clock stepping), with a special purpose "qtest" protocol. Refer to the -documentation in ``qtest.c`` for more details of the protocol. +clock stepping), with a special purpose "qtest" protocol. Refer to +:ref:`qtest-protocol` for more details of the protocol. QTest cases can be executed with @@ -56,3 +56,11 @@ from the output of which you can run manually. + +.. _qtest-protocol: + +QTest Protocol +-------------- + +.. kernel-doc:: softmmu/qtest.c + :doc: QTest Protocol diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 4e439caec7e..9382fd25439 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -49,92 +49,141 @@ static void *qtest_server_send_opaque; #define FMT_timeval "%ld.%06ld" /** - * QTest Protocol + * DOC: QTest Protocol + * + * .. highlight:: none * * Line based protocol, request/response based. Server can send async messages * so clients should always handle many async messages before the response * comes in. * * Valid requests + * ^^^^^^^^^^^^^^ * * Clock management: + * """"""""""""""""" * * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands * let you adjust the value of the clock (monotonically). All the commands * return the current value of the clock in nanoseconds. * + * .. code-block:: + * * > clock_step * < OK VALUE * - * Advance the clock to the next deadline. Useful when waiting for - * asynchronous events. + * Advance the clock to the next deadline. Useful when waiting for + * asynchronous events. + * + * .. code-block:: * * > clock_step NS * < OK VALUE * - * Advance the clock by NS nanoseconds. + * Advance the clock by NS nanoseconds. + * + * .. code-block:: * * > clock_set NS * < OK VALUE * - * Advance the clock to NS nanoseconds (do nothing if it's already past). + * Advance the clock to NS nanoseconds (do nothing if it's already past). * * PIO and memory access: + * """""""""""""""""""""" + * + * .. code-block:: * * > outb ADDR VALUE * < OK * + * .. code-block:: + * * > outw ADDR VALUE * < OK * + * .. code-block:: + * * > outl ADDR VALUE * < OK * + * .. code-block:: + * * > inb ADDR * < OK VALUE * + * .. code-block:: + * * > inw ADDR * < OK VALUE * + * .. code-block:: + * * > inl ADDR * < OK VALUE * + * .. code-block:: + * * > writeb ADDR VALUE * < OK * + * .. code-block:: + * * > writew ADDR VALUE * < OK * + * .. code-block:: + * * > writel ADDR VALUE * < OK * + * .. code-block:: + * * > writeq ADDR VALUE * < OK * + * .. code-block:: + * * > readb ADDR * < OK VALUE * + * .. code-block:: + * * > readw ADDR * < OK VALUE * + * .. code-block:: + * * > readl ADDR * < OK VALUE * + * .. code-block:: + * * > readq ADDR * < OK VALUE * + * .. code-block:: + * * > read ADDR SIZE * < OK DATA * + * .. code-block:: + * * > write ADDR SIZE DATA * < OK * + * .. code-block:: + * * > b64read ADDR SIZE * < OK B64_DATA * + * .. code-block:: + * * > b64write ADDR SIZE B64_DATA * < OK * + * .. code-block:: + * * > memset ADDR SIZE VALUE * < OK * @@ -149,16 +198,21 @@ static void *qtest_server_send_opaque; * If the sizes do not match, the data will be truncated. * * IRQ management: + * """"""""""""""" + * + * .. code-block:: * * > irq_intercept_in QOM-PATH * < OK * + * .. code-block:: + * * > irq_intercept_out QOM-PATH * < OK * * Attach to the gpio-in (resp. gpio-out) pins exported by the device at * QOM-PATH. When the pin is triggered, one of the following async messages - * will be printed to the qtest stream: + * will be printed to the qtest stream:: * * IRQ raise NUM * IRQ lower NUM @@ -168,12 +222,15 @@ static void *qtest_server_send_opaque; * NUM=0 even though it is remapped to GSI 2). * * Setting interrupt level: + * """""""""""""""""""""""" + * + * .. code-block:: * * > set_irq_in QOM-PATH NAME NUM LEVEL * < OK * - * where NAME is the name of the irq/gpio list, NUM is an IRQ number and - * LEVEL is an signed integer IRQ level. + * where NAME is the name of the irq/gpio list, NUM is an IRQ number and + * LEVEL is an signed integer IRQ level. * * Forcibly set the given interrupt pin to the given level. *