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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y66sm7095961wmd.14.2020.10.12.08.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 08:37:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension Date: Mon, 12 Oct 2020 16:37:45 +0100 Message-Id: <20201012153746.9996-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201012153746.9996-1-peter.maydell@linaro.org> References: <20201012153746.9996-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" If the M-profile low-overhead-branch extension is implemented, FPSCR bits [18:16] are a new field LTPSIZE. If MVE is not implemented (currently always true for us) then this field always reads as 4 and ignores writes. These bits used to be the vector-length field for the old short-vector extension, so we need to take care that they are not misinterpreted as setting vec_len. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 5 +++++ target/arm/vfp_helper.c | 25 +++++++++++++++++++++---- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 186ee621a65..baae826f94f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -255,6 +255,11 @@ static void arm_cpu_reset(DeviceState *dev) uint8_t *rom; uint32_t vecbase; + if (cpu_isar_feature(aa32_lob, cpu)) { + /* LTPSIZE is constant 4 if MVE not implemented */ + env->vfp.xregs[ARM_VFP_FPSCR] |= 4 << 16; + } + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { env->v7m.secure = true; } else { diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 5666393ef79..350150adbf1 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -189,8 +189,10 @@ uint32_t vfp_get_fpscr(CPUARMState *env) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { + ARMCPU *cpu = env_archcpu(env); + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, cpu)) { val &= ~FPCR_FZ16; } @@ -198,8 +200,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) /* * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits * and also for the trapped-exception-handling bits IxE. + * From v8.1M with the low-overhead-loop extension bits + * [18:16] are used for LTPSIZE and (since we don't implement + * MVE) always read as 4 and ignore writes. */ val &= 0xf7c0009f; + if (cpu_isar_feature(aa32_lob, cpu)) { + val |= 4 << 16; + } } vfp_set_fpscr_to_host(env, val); @@ -212,9 +220,18 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) * (which are stored in fp_status), and the other RES0 bits * in between, then we clear all of the low 16 bits. */ - env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000; - env->vfp.vec_len = (val >> 16) & 7; - env->vfp.vec_stride = (val >> 20) & 3; + if (cpu_isar_feature(aa32_lob, cpu)) { + /* + * M-profile low-overhead-loop extension: [18:16] are LTPSIZE + * and we keep them in vfp.xregs[]. + */ + env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7cf0000; + } else { + /* Those bits might be the old-style short vector length/stride */ + env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000; + env->vfp.vec_len = (val >> 16) & 7; + env->vfp.vec_stride = (val >> 20) & 3; + } /* * The bit we set within fpscr_q is arbitrary; the register as a