diff mbox series

[RFC,v2,3/4] target/mips: Make the number of TLB entries a CPU property

Message ID 20201015224746.540027-4-f4bug@amsat.org
State New
Headers show
Series target/mips: Make the number of TLB entries a CPU property | expand

Commit Message

Philippe Mathieu-Daudé Oct. 15, 2020, 10:47 p.m. UTC 
Allow selecting the number of TLB entries from a preset array.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/internal.h  |  1 +
 target/mips/cpu.c       |  8 +++++++-
 target/mips/translate.c | 26 ++++++++++++++++++++++++--
 3 files changed, 32 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/target/mips/internal.h b/target/mips/internal.h
index c2b2e79c515..34f82c6e842 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -29,6 +29,7 @@  struct mips_def_t {
     int32_t CP0_PRid;
     int32_t CP0_Config0;
     int32_t CP0_Config1;
+    const unsigned *CP0_Config1_MMU_preset;
     int32_t CP0_Config2;
     int32_t CP0_Config3;
     int32_t CP0_Config4;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 117c748345e..da31831368b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -26,7 +26,7 @@ 
 #include "qemu/module.h"
 #include "sysemu/kvm.h"
 #include "exec/exec-all.h"
-
+#include "hw/qdev-properties.h"
 
 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 {
@@ -183,6 +183,11 @@  static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
     return oc;
 }
 
+static Property mips_cpu_properties[] = {
+    DEFINE_PROP_UINT8("tlb-entries", MIPSCPU, env.tlb_entries, 0),
+    DEFINE_PROP_END_OF_LIST()
+};
+
 static void mips_cpu_class_init(ObjectClass *c, void *data)
 {
     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
@@ -192,6 +197,7 @@  static void mips_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_parent_realize(dc, mips_cpu_realizefn,
                                     &mcc->parent_realize);
     device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
+    device_class_set_props(dc, mips_cpu_properties);
 
     cc->class_by_name = mips_cpu_class_by_name;
     cc->has_work = mips_cpu_has_work;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 698bcee8915..f5815160fb6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -39,6 +39,7 @@ 
 #include "exec/translator.h"
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
+#include "qapi/error.h"
 
 #define MIPS_DEBUG_DISAS 0
 
@@ -31318,9 +31319,30 @@  void mips_tcg_init(void)
 
 static bool init_tlb_entries(CPUMIPSState *env, Error **errp)
 {
-    env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6);
+    const unsigned *preset = env->cpu_model->CP0_Config1_MMU_preset;
+    bool valid = false;
 
-    return true;
+    if (!env->tlb_entries) {
+        env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1,
+                                         CP0C1_MMU, 6);
+        return true;
+    }
+    if (!preset) {
+        error_setg(errp, "Property 'tlb-entries' not modifiable for this CPU");
+        return false;
+    }
+    while (!valid && *preset) {
+        if (*preset == env->tlb_entries) {
+            valid = true;
+            break;
+        }
+        preset++;
+    }
+    if (!valid) {
+        error_setg(errp, "Invalid value '%u' for property 'tlb-entries'",
+                   env->tlb_entries);
+    }
+    return valid;
 }
 
 bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp)