@@ -30,6 +30,7 @@
#include "hw/mips/cps.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci-host/xilinx-pcie.h"
+#include "hw/qdev-clock.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
@@ -54,6 +55,7 @@ struct BostonState {
MachineState *mach;
MIPSCPSState cps;
SerialMM *uart;
+ Clock *cpuclk;
CharBackend lcd_display;
char lcd_content[8];
@@ -251,10 +253,19 @@ static const MemoryRegionOps boston_platreg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void mips_boston_instance_init(Object *obj)
+{
+ BostonState *s = BOSTON(obj);
+
+ s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
+ clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */
+}
+
static const TypeInfo boston_device = {
.name = TYPE_MIPS_BOSTON,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BostonState),
+ .instance_init = mips_boston_instance_init,
};
static void boston_register_types(void)
@@ -462,6 +473,8 @@ static void boston_mach_init(MachineState *machine)
&error_fatal);
object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus,
&error_fatal);
+ qdev_connect_clock_in(DEVICE(&s->cps), "clk-in",
+ qdev_get_clock_out(dev, "cpu-refclk"));
sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
The I6400 can run at 1 GHz or more. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-19-f4bug@amsat.org> --- hw/mips/boston.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)