From patchwork Wed Oct 21 17:08:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 302364 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25780C388F9 for ; Wed, 21 Oct 2020 17:14:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 744962224E for ; Wed, 21 Oct 2020 17:14:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RBPepdQz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 744962224E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVHgh-0006BQ-EK for qemu-devel@archiver.kernel.org; Wed, 21 Oct 2020 13:14:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVHba-0001J1-Vr for qemu-devel@nongnu.org; Wed, 21 Oct 2020 13:08:54 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:55444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kVHbZ-0002Ly-2x for qemu-devel@nongnu.org; Wed, 21 Oct 2020 13:08:54 -0400 Received: by mail-wm1-x342.google.com with SMTP id a72so2918450wme.5 for ; Wed, 21 Oct 2020 10:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H1zBaXIPUFkoRX522wNIGvBuniNlrLtU+nW3sIqZkhk=; b=RBPepdQz9kw2Kch54mcIFJd9NEI5anhJJEJbjGHVrh8qJXr8Gk7VKjH9h0PNKMxJsL /yjP6bQUVRR3d0dOEva2zh9Km3dKMBUbhJx1bJDsqPdZ0jqh8chRuIYKwnnEEiFA1b1G kg5s+xFPuXoisq+dpl2NwDP3yzVQoBDPY+7LPBT5duV6sDJe+lFkcxWDNp8t1ktjV2rV Yz6huyaeCz6leOqAXx+I8YXzIbw3rAiPdt4kMslLOSMVgYsTumquYEeymW2N4XNlZvlV y/UZNTJ4fu1m9LIWwxVMGa6Oa6xWGucNyNyz16zOoUa6B0y/4OfLRv3xB9BKpRWUY1Rq 5bDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H1zBaXIPUFkoRX522wNIGvBuniNlrLtU+nW3sIqZkhk=; b=BD9AoYIZIiUnirFbXNFptRJ+0B8GKWs9TRM7myaQxbOYwRfZF0u+E2U+Q/hNAMHZmH r1fjJ+dFMtv0pwJ/Cw+P3H45HZXxLw6AL9dSu18gK+Gd9tilNnmocIk3h7o0Dtddtyt5 iGem2I7z68EUgeZG8XyRj2nDWI4owTv4M5cxCUhLNQ658EMO55GRHLGGo1Wy7AixViPA OcOLBVN0eSapPIJnj+l/B+XnFRgIwpe2ilHUTvbI68wAnRtfAMRbkPUd5DRC5vHAmapF RFLxhgNvrFA0n2+mIi2y0PEPnk/qHqHAWdeu3EcD6GvV0KRVcoa30tuTSV5YPgK7TPyc wtPw== X-Gm-Message-State: AOAM531Nra51f5Od0FWJSFWaDHQF4XKM5v7+BUDlPgLxR24YJf6qXr4G pCl2LBwDa8GHrIs5ic3VunJRAw== X-Google-Smtp-Source: ABdhPJztTxmd4J+aGRrRXnwDl/57unRcgNdCJ8looxP28yeJjAttTIAgMuf0i4rt7IRBtskkk7r4YQ== X-Received: by 2002:a1c:66d5:: with SMTP id a204mr4474374wmc.62.1603300131688; Wed, 21 Oct 2020 10:08:51 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c130sm4503880wma.17.2020.10.21.10.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2020 10:08:44 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1D4AF1FF8C; Wed, 21 Oct 2020 18:08:43 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v1 2/4] hw/riscv: migrate fdt field to generic MachineState Date: Wed, 21 Oct 2020 18:08:40 +0100 Message-Id: <20201021170842.25762-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201021170842.25762-1-alex.bennee@linaro.org> References: <20201021170842.25762-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien@xen.org, Sagar Karandikar , masami.hiramatsu@linaro.org, andre.przywara@arm.com, stefano.stabellini@linaro.org, takahiro.akashi@linaro.org, Palmer Dabbelt , Bastian Koppelmann , Alistair Francis , stefano.stabellini@xilinx.com, =?utf-8?q?Alex_Benn=C3=A9e?= , "open list:RISC-V TCG CPUs" , stratos-dev@op-lists.linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a mechanical change to make the fdt available through MachineState. Signed-off-by: Alex Bennée Reviewed-by: Alistair Francis --- include/hw/riscv/virt.h | 1 - hw/riscv/virt.c | 18 +++++++++--------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b4ed9a32eb..6505ae8d23 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -41,7 +41,6 @@ struct RISCVVirtState { DeviceState *plic[VIRT_SOCKETS_MAX]; PFlashCFI01 *flash[2]; - void *fdt; int fdt_size; }; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 41bd2f38ba..17c0706156 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -194,7 +194,7 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; - fdt = s->fdt = create_device_tree(&s->fdt_size); + fdt = mc->fdt = create_device_tree(&s->fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -434,12 +434,12 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, g_free(name); name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(s->fdt, name); - qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); + qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); g_free(name); } @@ -613,9 +613,9 @@ static void virt_machine_init(MachineState *machine) hwaddr end = riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", end); } } else { @@ -636,11 +636,11 @@ static void virt_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, s->fdt); + machine->ram_size, machine->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, virt_memmap[VIRT_MROM].size, kernel_entry, - fdt_load_addr, s->fdt); + fdt_load_addr, machine->fdt); /* SiFive Test MMIO device */ sifive_test_create(memmap[VIRT_TEST].base);