diff mbox series

[PULL,18/26] hw/arm/boot: fix SVE for EL3 direct kernel boot

Message ID 20201102171005.30690-19-peter.maydell@linaro.org
State Not Applicable
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell Nov. 2, 2020, 5:09 p.m. UTC 
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>


When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so
that SVE will not trap to EL3.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20201030151541.11976-1-remi@remlab.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 hw/arm/boot.c | 3 +++
 1 file changed, 3 insertions(+)

-- 
2.20.1
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Patch

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 3e9816af803..cf97600a915 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -742,6 +742,9 @@  static void do_cpu_reset(void *opaque)
                     if (cpu_isar_feature(aa64_mte, cpu)) {
                         env->cp15.scr_el3 |= SCR_ATA;
                     }
+                    if (cpu_isar_feature(aa64_sve, cpu)) {
+                        env->cp15.cptr_el[3] |= CPTR_EZ;
+                    }
                     /* AArch64 kernels never boot in secure mode */
                     assert(!info->secure_boot);
                     /* This hook is only supported for AArch32 currently: