From patchwork Fri Nov 6 03:28:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 320735 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp979335ilc; Thu, 5 Nov 2020 19:37:19 -0800 (PST) X-Google-Smtp-Source: ABdhPJxPpLHhNFUlQ5ch1Q5Chv8+tVFbgDJ7B7wfZVsQ/06+Uyih1hWUgLKUUGdE6mZFLpMn1DwU X-Received: by 2002:a25:d442:: with SMTP id m63mr184002ybf.441.1604633839550; Thu, 05 Nov 2020 19:37:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604633839; cv=none; d=google.com; s=arc-20160816; b=oA/73ZMjQxrf/dSGVtoPnAoaz8Mh3ObG5Bdye6/XGzI+eB6xLHS4BvDm4B8cif382H BFPYMIwtYWTWt0roH3ZK9ZGDYQv/sa32oxZFXNAN+/nLrCi3hMq0DZ0XDWk1Bpeb1ojk A8Glak1zXFipS5f5vhHbVl8QeZfPK/RCQeRx8tBNyRKuEwxF275f1eURip2YB+nTk3Sn TZ4JC+ve43wEhjkhkbG1EXmGOx0wvXw2znB80/Wlp5o/PqophDPT6z3IleUDlX1jWJiq WamlFZGfWO854odF0Z/8GASlXOo2OaPU8WAA5DYPcRJe5fH5QWW/Y849d7bhaPP0Xc7M gp6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PE5zDJYupwBF6LFLJEA3Vgnp30HPDgVW1boJkF7byFo=; b=OGYOdJ4lv6mYQRhilrzdQkZebiVabADztvhag4xvjshSCC7N/KfyP/lnOfu6vK0hJc kQa0ZCXOL2O7K0G873uwLkV8h+fFz2U0lRC4b0X0R5nL5iqbwzKw7Jt5SxCoQ+cO1TKy 33I+bW4Sz+kcnP9OfAgW6Wn8K61R8gGz/1QHBWe78ORC1PtUz5zSNjdWpVSmQQKlnzl4 MOO/Kodj7Vqso5Jl/txfI9CGdBP1E3LuU3bLJLg6kSfMMz7iF1crhrhzusA2sTNDYRJL 5J5zO/H9HvzNIEi0P2eC2aQm7iqOqf1U+M5X9CiS2ck/cF7sXjbMAlrVVLOsKKQ4KFDv LIUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nh1h5Cqr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m11si2852946ybk.20.2020.11.05.19.37.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 05 Nov 2020 19:37:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nh1h5Cqr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kasYw-0006Uk-Vi for patch@linaro.org; Thu, 05 Nov 2020 22:37:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kasRg-0004ve-UZ for qemu-devel@nongnu.org; Thu, 05 Nov 2020 22:29:48 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:38583) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kasRe-0006xk-Te for qemu-devel@nongnu.org; Thu, 05 Nov 2020 22:29:48 -0500 Received: by mail-pl1-x635.google.com with SMTP id f21so26185plr.5 for ; Thu, 05 Nov 2020 19:29:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PE5zDJYupwBF6LFLJEA3Vgnp30HPDgVW1boJkF7byFo=; b=Nh1h5CqrdiO/dUF3trMOKu+s2Lhzmdg6eOQ5Sr8RJSinrg+WoGQ3uDI3T1EIudNskN qEEJ7BW/DCLDsU86p3ZZ7niofar2Kl6Fb1sAfTVOxn+00HUj5KiGntrs/Ixxipf48Gf5 YWY3pJYNdb8EzfWNCmvO+OOnr2yVOcW5gPVhQD8pmGxgK0L8mCj2jaRfj9RhtM4eI3fG 8WS1o51PB8aXd6QvasDVwqPbN6uM4aCf8mW0+Ay4irjPx7sUym+UdiRWYJEiTb58UyQa 3UUpMta4bhmaSUm/YSexHmzq0bN3o6VsAA7vtzeZePfwAtwGJlSqrwPobkIS0hEXZtJn rOKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PE5zDJYupwBF6LFLJEA3Vgnp30HPDgVW1boJkF7byFo=; b=RAdm6C9Xw5sK4VyGvYXNUROdvyYiMRqBifU7lm2y6EV4TzN1RCx+n5+La/vsvUJeIt j15zjZA7pXDfcotibWairnWulMtww5cbkRarhFA7edXrJA5KRUePOu/ycErOH8fF8oHk NnUZl0LH9iDCXNInhLsMswjRPjSYX8ymC1oHwS//rVeuAWxzqd14MJuOE9LKR1QSXbIw QvEVYwx7ulb4EM8WMz5vFo+DwDMz0aYCqNlcZj9IX/r1r6Y1UbbMBGDecdgYE2Gs2k7W t6TMrNjBNFFVtrxb90RCn0Ud9gV443FnQNlrO0NnZhBjc4gI8Usye4n71wEneUAvq02Q qufQ== X-Gm-Message-State: AOAM532Pd56JAB2oueChah3VgSnHyvEOWkI3zDxgy2L1ORXNh778eM3p RhvwYWEeu/G93mzSd/Oi5vRp8WSnMQ7dRA== X-Received: by 2002:a17:902:7c14:b029:d4:d894:7eed with SMTP id x20-20020a1709027c14b02900d4d8947eedmr7851pll.81.1604633385145; Thu, 05 Nov 2020 19:29:45 -0800 (PST) Received: from localhost.localdomain (76-14-210-194.or.wavecable.com. [76.14.210.194]) by smtp.gmail.com with ESMTPSA id i10sm40773pfd.60.2020.11.05.19.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2020 19:29:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/41] tcg: Return the TB pointer from the rx region from exit_tb Date: Thu, 5 Nov 2020 19:28:57 -0800 Message-Id: <20201106032921.600200-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201106032921.600200-1-richard.henderson@linaro.org> References: <20201106032921.600200-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: j@getutm.app Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This produces a small pc-relative displacement within the generated code to the TB structure that preceeds it. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 35 ++++++++++++++++++++++------------- tcg/tcg-op.c | 13 ++++++++++++- 2 files changed, 34 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 272d596e0c..8df0a1782e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -144,12 +144,13 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) #endif /* CONFIG USER ONLY */ /* Execute a TB, and fix up the CPU state afterwards if necessary */ -static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) +static inline TranslationBlock *cpu_tb_exec(CPUState *cpu, + TranslationBlock *itb, + int *tb_exit) { CPUArchState *env = cpu->env_ptr; uintptr_t ret; TranslationBlock *last_tb; - int tb_exit; const void *tb_ptr = itb->tc.ptr; qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, @@ -177,11 +178,20 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) ret = tcg_qemu_tb_exec(env, tb_ptr); cpu->can_do_io = 1; - last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); - tb_exit = ret & TB_EXIT_MASK; - trace_exec_tb_exit(last_tb, tb_exit); + /* + * TODO: Delay swapping back to the read-write region of the TB + * until we actually need to modify the TB. The read-only copy, + * coming from the rx region, shares the same host TLB entry as + * the code that executed the exit_tb opcode that arrived here. + * If we insist on touching both the RX and the RW pages, we + * double the host TLB pressure. + */ + last_tb = tcg_splitwx_to_rw((void *)(ret & ~TB_EXIT_MASK)); + *tb_exit = ret & TB_EXIT_MASK; - if (tb_exit > TB_EXIT_IDX1) { + trace_exec_tb_exit(last_tb, *tb_exit); + + if (*tb_exit > TB_EXIT_IDX1) { /* We didn't start executing this TB (eg because the instruction * counter hit zero); we must restore the guest PC to the address * of the start of the TB. @@ -199,7 +209,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) cc->set_pc(cpu, last_tb->pc); } } - return ret; + return last_tb; } #ifndef CONFIG_USER_ONLY @@ -210,6 +220,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles, { TranslationBlock *tb; uint32_t cflags = curr_cflags() | CF_NOCACHE; + int tb_exit; if (ignore_icount) { cflags &= ~CF_USE_ICOUNT; @@ -227,7 +238,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles, /* execute the generated code */ trace_exec_tb_nocache(tb, tb->pc); - cpu_tb_exec(cpu, tb); + cpu_tb_exec(cpu, tb, &tb_exit); mmap_lock(); tb_phys_invalidate(tb, -1); @@ -244,6 +255,7 @@ void cpu_exec_step_atomic(CPUState *cpu) uint32_t flags; uint32_t cflags = 1; uint32_t cf_mask = cflags & CF_HASH_MASK; + int tb_exit; if (sigsetjmp(cpu->jmp_env, 0) == 0) { start_exclusive(); @@ -260,7 +272,7 @@ void cpu_exec_step_atomic(CPUState *cpu) cc->cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); - cpu_tb_exec(cpu, tb); + cpu_tb_exec(cpu, tb, &tb_exit); cc->cpu_exec_exit(cpu); } else { /* @@ -653,13 +665,10 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, TranslationBlock **last_tb, int *tb_exit) { - uintptr_t ret; int32_t insns_left; trace_exec_tb(tb, tb->pc); - ret = cpu_tb_exec(cpu, tb); - tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); - *tb_exit = ret & TB_EXIT_MASK; + tb = cpu_tb_exec(cpu, tb, tb_exit); if (*tb_exit != TB_EXIT_REQUESTED) { *last_tb = tb; return; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e3dc0cb4cb..56bb8db040 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2666,7 +2666,18 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) { - uintptr_t val = (uintptr_t)tb + idx; + /* + * Let the jit code return the read-only version of the + * TranslationBlock, so that we minimize the pc-relative + * distance of the address of the exit_tb code to TB. + * This will improve utilization of pc-relative address loads. + * + * TODO: Move this to translator_loop, so that all const + * TranslationBlock pointers refer to read-only memory. + * This requires coordination with targets that do not use + * the translator_loop. + */ + uintptr_t val = (uintptr_t)tcg_splitwx_to_rx((void *)tb) + idx; if (tb == NULL) { tcg_debug_assert(idx == 0);