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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id w11sm11844123pge.28.2020.12.24.14.45.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Dec 2020 14:45:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec Date: Thu, 24 Dec 2020 14:45:13 -0800 Message-Id: <20201224224514.626561-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201224224514.626561-1-richard.henderson@linaro.org> References: <20201224224514.626561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-conset.h | 1 + tcg/arm/tcg-target.opc.h | 1 + tcg/arm/tcg-target.c.inc | 15 +++++++++++++++ 3 files changed, 17 insertions(+) -- 2.25.1 diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h index 30a5953621..efb63396de 100644 --- a/tcg/arm/tcg-target-conset.h +++ b/tcg/arm/tcg-target-conset.h @@ -25,6 +25,7 @@ C_O1_I2(r, r, rIK) C_O1_I2(r, r, rIN) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, rZ) +C_O1_I2(w, 0, w) C_O1_I2(w, w, w) C_O1_I2(w, w, wO) C_O1_I2(w, w, wV) diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h index d19153dcb9..d38af9a808 100644 --- a/tcg/arm/tcg-target.opc.h +++ b/tcg/arm/tcg-target.opc.h @@ -11,5 +11,6 @@ * consider these to be UNSPEC with names. */ +DEF(arm_sli_vec, 1, 2, 1, IMPLVEC) DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC) DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2a664a750d..5cae6b2749 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -215,6 +215,7 @@ typedef enum { INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ INSN_VSARI = 0xf2800010, /* VSHR.S */ INSN_VSHRI = 0xf3800010, /* VSHR.U */ + INSN_VSLI = 0xf3800510, INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ @@ -2400,6 +2401,8 @@ static int tcg_target_op_def(TCGOpcode op) case INDEX_op_arm_sshl_vec: case INDEX_op_arm_ushl_vec: return C_O1_I2(w, w, w); + case INDEX_op_arm_sli_vec: + return C_O1_I2(w, 0, w); case INDEX_op_or_vec: case INDEX_op_andc_vec: return C_O1_I2(w, w, wO); @@ -2815,6 +2818,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_sari_vec: tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); return; + case INDEX_op_arm_sli_vec: + tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); + return; case INDEX_op_andc_vec: if (!const_args[2]) { @@ -2943,6 +2949,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotli_vec: return -1; default: return 0; @@ -2988,6 +2995,14 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, tcg_temp_free_vec(t1); break; + case INDEX_op_rotli_vec: + t1 = tcg_temp_new_vec(type); + tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); + vec_gen_4(INDEX_op_arm_sli_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); + tcg_temp_free_vec(t1); + break; + default: g_assert_not_reached(); }