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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id w11sm11844123pge.28.2020.12.24.14.45.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Dec 2020 14:45:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types Date: Thu, 24 Dec 2020 14:45:01 -0800 Message-Id: <20201224224514.626561-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201224224514.626561-1-richard.henderson@linaro.org> References: <20201224224514.626561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 64 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 48966da12f..7122d5f390 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -175,6 +175,9 @@ typedef enum { INSN_NOP_v6k = 0xe320f000, /* Otherwise the assembler uses mov r0,r0 */ INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, + + INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ + INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ } ARMInsn; #define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) @@ -1073,6 +1076,33 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, } } +/* + * Note that TCGReg references Q-registers. + * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting. + */ +static uint32_t encode_vd(TCGReg rd) +{ + tcg_debug_assert(rd >= TCG_REG_Q0); + return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); +} + +static void tcg_out_vldst(TCGContext *s, ARMInsn insn, + TCGReg rd, TCGReg rn, int offset) +{ + if (offset != 0) { + if (check_fit_imm(offset) || check_fit_imm(-offset)) { + tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, + TCG_REG_TMP, rn, offset, true); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_TMP, TCG_REG_TMP, rn, 0); + } + rn = TCG_REG_TMP; + } + tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); +} + #ifdef CONFIG_SOFTMMU #include "../tcg-ldst.c.inc" @@ -2184,16 +2214,44 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); } -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { - tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); + switch (type) { + case TCG_TYPE_I32: + tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); + return; + case TCG_TYPE_V64: + /* regs 1; size 8; align 8 */ + tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); + return; + case TCG_TYPE_V128: + /* regs 2; size 8; align 16 */ + tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2); + return; + default: + g_assert_not_reached(); + } } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { - tcg_out_st32(s, COND_AL, arg, arg1, arg2); + switch (type) { + case TCG_TYPE_I32: + tcg_out_st32(s, COND_AL, arg, arg1, arg2); + return; + case TCG_TYPE_V64: + /* regs 1; size 8; align 8 */ + tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); + return; + case TCG_TYPE_V128: + /* regs 2; size 8; align 16 */ + tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2); + return; + default: + g_assert_not_reached(); + } } static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,