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[209.51.188.17]) by mx.google.com with ESMTPS id b15si7369161ybn.473.2021.01.15.06.30.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Jan 2021 06:30:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="bpee/CyJ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l0Q7i-0003mx-Il for patch@linaro.org; Fri, 15 Jan 2021 09:30:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0PEU-000130-9r for qemu-devel@nongnu.org; Fri, 15 Jan 2021 08:33:42 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:42782) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0PER-00083z-UJ for qemu-devel@nongnu.org; Fri, 15 Jan 2021 08:33:42 -0500 Received: by mail-wr1-x429.google.com with SMTP id m4so9280939wrx.9 for ; Fri, 15 Jan 2021 05:33:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z7qx5BbOQ9U2pOy58BttUDuc3hCnuco/Gmd85qnIRTs=; b=bpee/CyJRZtyEZa+9BFSzPp1fJUAe/SlJ8SRKAgZ5HPFEf8xyX0Pm/u6sCCaNcglTm /htzKpiJ2u5Dy6zXzp1BYC1XYl2qXbzUl7PEv3p2CB5t/X9ibgh3AISzXUVIceufu88/ BoNtAdQV2et1uUppoRTUw6Vl03fy2Yug9xOzhOa9zRVsUZsP07DpALvcA0hZVzuE4q20 UgRicMYU+OPR+mDa1z2GAUmw2svBqgU3oCiXxcL9Xc6o9b9RCVo7Hhc4MZwUwPEtT9I4 SIRG2j/xxjsaiH13Zyc7Qn550MBPW/oam33R9bp7vrqKLY0m2P7Xn3IJPJ/guKOLrsvf oNdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z7qx5BbOQ9U2pOy58BttUDuc3hCnuco/Gmd85qnIRTs=; b=bsVCCtZQvtQVVicVOBnY0KBJGKtmBoAgf1Xx2IItbHxG4v++2U7a0QxYaQCkF6bJGf rojyqray7b1CNkXipAwu0sOkSSvyj0iuCDHgDZZHdL2xc1/CdfdCqRxJ2WRPoImffk9C 6szeBtpXLvM6Y4FoTgyNd/p+1F8h+rretOwaOkn4MOiNWmUKwoVnNcFusiDGoa31q9L0 NJdGZGh5nfADt+kSn1gEBIM0o48jfWmyxjXNLK5kauO7L1/5GJjZOnbR/e9WPwtXugQS ePXcmNZ6lofGTwKkpTn0WFCm5s4ota6zLHVWQEQvRj/g0h4ZxGXd7g7l0NCgnGjEuQ8L EE9A== X-Gm-Message-State: AOAM532oxXF4PO4wTR5UkcsptoMGG8S9dY/S8azOM1Yn2OEgTjMxnvpz ud18uHZpp1DaOu7/7rIy9+1gmQ== X-Received: by 2002:adf:9d48:: with SMTP id o8mr13342904wre.408.1610717618549; Fri, 15 Jan 2021 05:33:38 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id u83sm12813287wmu.12.2021.01.15.05.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 05:33:33 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 006961FFAC; Fri, 15 Jan 2021 13:08:34 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Subject: [PULL 23/30] semihosting: Change common-semi API to be architecture-independent Date: Fri, 15 Jan 2021 13:08:21 +0000 Message-Id: <20210115130828.23968-24-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115130828.23968-1-alex.bennee@linaro.org> References: <20210115130828.23968-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Packard , qemu-devel@nongnu.org, Laurent Vivier , "open list:ARM TCG CPUs" , Alistair Francis , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Keith Packard The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard Signed-off-by: Alex Bennée Reviewed-by: Alistair Francis Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org> -- 2.20.1 diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h new file mode 100644 index 0000000000..bc53e92c79 --- /dev/null +++ b/hw/semihosting/common-semi.h @@ -0,0 +1,36 @@ +/* + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019 Linaro + * Written by Paul Brook. + * + * Copyright © 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * + * ARM Semihosting is documented in: + * Semihosting for AArch32 and AArch64 Release 2.0 + * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + */ + +#ifndef COMMON_SEMI_H +#define COMMON_SEMI_H + +target_ulong do_common_semihosting(CPUState *cs); + +#endif /* COMMON_SEMI_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f3bca73d98..84cc2de3b1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1068,14 +1068,6 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, static inline void aarch64_add_sve_properties(Object *obj) { } #endif -#if !defined(CONFIG_TCG) -static inline target_ulong do_arm_semihosting(CPUARMState *env) -{ - g_assert_not_reached(); -} -#else -target_ulong do_arm_semihosting(CPUARMState *env); -#endif void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); diff --git a/hw/semihosting/arm-compat-semi.c b/hw/semihosting/arm-compat-semi.c index 93360e28c7..2e959aba08 100644 --- a/hw/semihosting/arm-compat-semi.c +++ b/hw/semihosting/arm-compat-semi.c @@ -1,10 +1,14 @@ /* - * Arm "Angel" semihosting syscalls + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro * Written by Paul Brook. * + * Copyright © 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -373,12 +377,12 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do anything with its return value, because it is not necessarily * the result of the syscall, but could just be the old value of X0. * The only thing safe to do with this is that the callers of - * do_arm_semihosting() will write it straight back into X0. + * do_common_semihosting() will write it straight back into X0. * (In linux-user mode, the callback will have happened before * gdb_do_syscallv() returns.) * * We should tidy this up so neither this function nor - * do_arm_semihosting() return a value, so the mistake of + * do_common_semihosting() return a value, so the mistake of * doing something with the return value is not possible to make. */ @@ -675,10 +679,10 @@ static const GuestFDFunctions guestfd_fns[] = { * leave the register unchanged. We use 0xdeadbeef as the return value * when there isn't a defined return value for the call. */ -target_ulong do_arm_semihosting(CPUARMState *env) +target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = env_cpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..42b9c15f53 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -129,7 +130,7 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; break; case EXCP_YIELD: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 3d272b56ef..cadfb7fa43 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -421,7 +422,7 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_SEMIHOST: - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: diff --git a/target/arm/helper.c b/target/arm/helper.c index 8a492465d6..c5377e7ecb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -9875,13 +9876,13 @@ static void handle_semihosting(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; } } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 643dcafb83..6176003029 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -31,6 +31,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, @@ -2306,7 +2307,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); +#ifdef CONFIG_TCG + env->regs[0] = do_common_semihosting(cs); +#else + g_assert_not_reached(); +#endif env->regs[15] += env->thumb ? 2 : 4; return; case EXCP_BKPT: