From patchwork Wed Feb 3 02:15:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 375370 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp738280jah; Tue, 2 Feb 2021 18:33:12 -0800 (PST) X-Google-Smtp-Source: ABdhPJxpPq/osLr0ChCNOJYamMOsDxFFsaL6B4AzXCN3gLqelwk6Lkx5y0eoaZ+qovuQRneOWAkX X-Received: by 2002:a25:264b:: with SMTP id m72mr1372642ybm.486.1612319592317; Tue, 02 Feb 2021 18:33:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612319592; cv=none; d=google.com; s=arc-20160816; b=oI9+q9DGrSUfQ/7I0ARLzjogIt0WWS8dVoovTm14Cv3Cqb5Vrmob8kW/gqlJx9n2WO XdIigRGr1VGZqmC5oeTNkdDtHX4liCy3FL2OWJ6Xb1N4OuBqCrDlpdm8htiOraImgJd5 uB8GCmURbqMMdczr8TkEtGTpXdr7tVVx837Lvxu9esZ2/A/ZnzETnZ+eDajS2TaNr69j qI5MjqbBiVAldZxV/mfXHxp6X7lSHJ0L6xXweJyppTtTqhQoP7Yk/tvR0tkaVTVBeJan OFAxLT07XEjc0z0NNVhzXAFwdl5bHBMoRl/dk3V3qn+2bqr5XW4ceBZxnGy12JT9IECP Q/JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dgFs0kRvG3YRS9ydc6sjoVZGH6LkBq65P9PIXpXmt7w=; b=AqcFf6LF9PJ4Njd7AstXN5/8qk38WLMGaVncjRvCkaJzi9ALXjc7ngF8vQZosSpxhH IeYeMa+EYo1fZCNW4Zl7sB/b7TnaTOkuJlGBVA9AAPULpc5cSNTqlj6ZIk5OtdXOllFZ 9ildLQCr04ME6pBB7w5R6b0tp4zHkfJ5erEgiMJtzglnq0nZOG7TVnCpbisqG8wpC0JS mkzBpuun6Rcjz76/bTH6TbC4uyI0GPLpkEjmK5dlcqqcu3W4ySSnpu1SKrlK3s5RQq7S UTVL4xAcKBYOQXbGX6mvGY5nS98zOaR6ZySIvWpMw2uz0v7snPBEJqBW6rxxlb3InZiz 80NA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P34b+cJu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k1si782990ybm.38.2021.02.02.18.33.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 Feb 2021 18:33:12 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P34b+cJu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l77yh-0003as-PV for patch@linaro.org; Tue, 02 Feb 2021 21:33:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l77iV-0007yf-MD for qemu-devel@nongnu.org; Tue, 02 Feb 2021 21:16:27 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:35772) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l77iT-00015i-M7 for qemu-devel@nongnu.org; Tue, 02 Feb 2021 21:16:27 -0500 Received: by mail-pg1-x534.google.com with SMTP id t25so16252014pga.2 for ; Tue, 02 Feb 2021 18:16:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dgFs0kRvG3YRS9ydc6sjoVZGH6LkBq65P9PIXpXmt7w=; b=P34b+cJu0JGgF/uYikZHnbq11ZYvLFsAipc8Sya8/l4KGmdJUn4e9iT63LHyyjAUjw hn7qoDSLytPWinVox5k6sUdex6yzwlpacHp8YGkzSqOKJNtiCW90FWAiZO5cbU4dojDN KN8lGcxiCXWm6jAyqJpwcCubC8VeOWsqMG0XALv9WxVBIM+bmga17/e/D0l2I1jSxnia j01H+l8A/TC95TwoXv8tDLwPlZ09HjOb3vYslGeTFZsAiRyJiI1OE4u4QsUCkWPV+0qM GeEHFYgdlv7nWmWqII8nzHeV5tbujNADJGk6d4xFsvOOlmwqbs5yRhTgFA1C6JkpWCgp cu3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dgFs0kRvG3YRS9ydc6sjoVZGH6LkBq65P9PIXpXmt7w=; b=DZqxf0+IAQgombo9fo/RUyhUHQwAQUL5qd1ZhV9B13MHT1Fft+O3JVPz6a6uM9iOXh gDjMMeW3jR6kirqpeyDVZXkn7FMtke6CUnHXZKQ5vZpGEMIYg08sqPuiaTs5vkXPA/tl 4OaJtUgtJmub5sivF2+QaIdtbEMKKZuJnqQmTfVjJkzMaNIm1jUNs7KrFZTzkBUiVSmR x44bt8m16VUYMmTUZEQ3+Kcn+uh8WExeeeXKAHxiSSdv6UrpokRn/kPE9bzAAh2YOq1h 1A+TypJpkbEIQMgYNJ50hAHZyiCW6XHPMTsJczT59hWPoMmCwhTnwtXTdtsmoeLJZmos rbOg== X-Gm-Message-State: AOAM531fy6pLBrPLKRA40Ffws/mntp8sannNikno9REKoV34D1Bq0zyO hg1rRuIAxsoHttqxeK71R1ZC0a3bsQ7mVsnx X-Received: by 2002:a05:6a00:8d0:b029:1b6:3581:4f41 with SMTP id s16-20020a056a0008d0b02901b635814f41mr895329pfu.56.1612318584336; Tue, 02 Feb 2021 18:16:24 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id x1sm270301pgj.37.2021.02.02.18.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 18:16:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/24] tcg/riscv: Split out constraint sets to tcg-target-con-set.h Date: Tue, 2 Feb 2021 16:15:46 -1000 Message-Id: <20210203021550.375058-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210203021550.375058-1-richard.henderson@linaro.org> References: <20210203021550.375058-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 30 ++++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------ 3 files changed, 54 insertions(+), 60 deletions(-) create mode 100644 tcg/riscv/tcg-target-con-set.h -- 2.25.1 diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h new file mode 100644 index 0000000000..cf0ac4d751 --- /dev/null +++ b/tcg/riscv/tcg-target-con-set.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define RISC-V target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(LZ, L) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I3(LZ, L, L) +C_O0_I3(LZ, LZ, L) +C_O0_I4(LZ, LZ, L, L) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 727c8df418..a998b951e4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CON_SET_H #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 20d5b5ef01..e700c52067 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1543,50 +1543,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r - = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r - = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef rZ_r - = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef rZ_rZ - = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef rZ_rZ_rZ_rZ - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_ri - = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI - = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_L - = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef r_r_L - = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L - = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef LZ_L - = { .args_ct_str = { "LZ", "L" } }; - static const TCGTargetOpDef LZ_L_L - = { .args_ct_str = { "LZ", "L", "L" } }; - static const TCGTargetOpDef LZ_LZ_L - = { .args_ct_str = { "LZ", "LZ", "L" } }; - static const TCGTargetOpDef LZ_LZ_L_L - = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1618,7 +1579,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -1627,7 +1588,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -1637,11 +1598,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: @@ -1659,7 +1620,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_rem_i64: case INDEX_op_remu_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -1667,39 +1628,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &r_r_rZ_rZ_rM_rM; + return C_O2_I4(r, r, rZ, rZ, rM, rM); case INDEX_op_brcond2_i32: - return &rZ_rZ_rZ_rZ; + return C_O0_I4(rZ, rZ, rZ, rZ); case INDEX_op_setcond2_i32: - return &r_rZ_rZ_rZ_rZ; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L; + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return TCG_TARGET_REG_BITS == 64 ? &LZ_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L - : &LZ_LZ_L_L; + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L) + : C_O0_I4(LZ, LZ, L, L)); default: - return NULL; + g_assert_not_reached(); } }