From patchwork Mon Feb 8 02:36:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378426 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4308171jah; Sun, 7 Feb 2021 18:39:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJzWmBMhSOCICU0InzhuIHMzgIoOmORCSnfmZYoAao3UC03wLIBR4LMEgkEIOGZASGuDb69v X-Received: by 2002:a25:7397:: with SMTP id o145mr23872922ybc.523.1612751978425; Sun, 07 Feb 2021 18:39:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612751978; cv=none; d=google.com; s=arc-20160816; b=Oj9V1vYSxk37z2PdTehHUQkcd99n+HTK5bPZ4yUDspQlYE5aV6i/DNpTRAQfJQp9SQ gnxhz534ln5KBLJSNrXThD5q0vAOSoMkOJXR8Es5iqfgOVnsOY3MwyAHgw90EO/mycgM TVXqBuFHLmRL1XRAs61NM0AHm57RUuNsjpUujSP2xkfXEi21j+24RcSS5M+/LzUhoEkh VmtBwrCrYIKkQLI6Qi6bcSUZF9L84HBn0Aedb+nt7b4ujvoS5nilDj6PMOcm9sZuzcuF neD8sEUN+/YTHaaaIP7DdgkNH4cfDcPc2iy9iMwC36pUJVN7KopKEVTwuSKAfmAGIepp KzwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=dM1s5vL32gLaQnbs4CwNKs/8W57wTtFLRPifjYJzSsVFzzG5PhE8FBLhn+CVIaUYPK FzwFhMzD8cP63ml0nUbZTtim3Bcb1zGTId7iALx05qVJm4rH/Vxb377A9Y02UZIKl+gN 6yoiP+6CVcG00kSuia/mgau9llNHLnjRLI4H6UYXcMxmV6yOR6ElYK8rkzS176T1bygv mAqMw9aw74W0Rr345rxeSLiNevhFAZwoCTaViKEmk9P4nsBmY1QgO1UPEzAx4w9iFgFQ 34rFXhTfvOrUpI1YKCqZs86WNTL+WfnkVuVjdI1Tp+PJSsuEqtJQmL9eFmiM8NY/4h7o ZSBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kUgTCcYQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f81si1408821yba.148.2021.02.07.18.39.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 07 Feb 2021 18:39:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kUgTCcYQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wSf-0001B4-Ok for patch@linaro.org; Sun, 07 Feb 2021 21:39:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRB-00017b-9l for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:05 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:40849) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wR9-0005iK-Lk for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:05 -0500 Received: by mail-pl1-x62a.google.com with SMTP id y10so7018885plk.7 for ; Sun, 07 Feb 2021 18:38:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=kUgTCcYQ0K/MS0zvZUBPNlcNLrKrsRDQN11BeVg84JX29lK5q4ErlNDB+xXwhOAVuy p+9SOjmsWtTU9odnzsPVPtU/iXHN87SgIG5BSZPuh0ywjed61xvs0F4IiqQcqJWh74aq ZLVn4wOwi/6JOZInD5m1aQkLDtqF6WNftdvLju0tI0OuXZyo8WDCvR0kSv223QoG7jbj dol6seKxyNkKE5Spq6S9X1UZpymYejcnhTZv1aldhoWo1EjxMllBRsLgj9LXlSyP3wGb ee8wVfOO120+MAld89lyEBQYUV5u6X5VtmzrinndjXt7XumhONs9bxVZ8kPiYFOXgAYT +yvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=muRPUtqNf5uyPHfbFjHwpyYty7LqpgFwvi1139wVYEZV2Yz779kIJioFe5W+dNPTpP jo9BCTCvAAhl/4W4tA+AvFMbjPyOFDntSXPaqs3FA42RsOVw7HU2HHjHxkBiBd15xLrF JaLCpN3YEs2FbHYZlu/Wr4q9SfvmcDlvRyNNxWkHyIi2FNx8zCOt7QeNXs/yED96pqDs beKr3mFx8KTkNVdhnEOzqVl6KK4GBAZtw5b7tHduT24BWq9ND6cRBpiPzB2lmbAwARCD PU41Vo88Y9RZTeMHN7DdG89Pu9NM9RS2ZhYahR3jS097lP64aq60rpMMTPCtYidyWUPn G8dA== X-Gm-Message-State: AOAM530K8YYohnlbtEQOGIPOYKd0nYcLnfgARHInbWLJxoF4tO8IoP2l 8eTtS72KOdAH+09cNmc+UFFI34FQwbaRUQ== X-Received: by 2002:a17:90a:d34b:: with SMTP id i11mr14627214pjx.235.1612751882411; Sun, 07 Feb 2021 18:38:02 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/70] tcg/tci: Remove tci_read_r8s Date: Sun, 7 Feb 2021 18:36:48 -0800 Message-Id: <20210208023752.270606-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext8s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index c44a4aec7b..25db479e62 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int8_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { @@ -164,16 +157,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -/* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - int8_t value = tci_read_reg8s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} -#endif - /* Read indexed register (16 bit) from bytecode. */ static uint16_t tci_read_r16(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -712,8 +695,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 = *tb_ptr++; - t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 @@ -927,8 +910,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 = *tb_ptr++; - t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64