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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id d84sm2070324qke.53.2021.03.11.06.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 06:40:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 10/57] tcg/tci: Split out tci_args_ri and tci_args_rI Date: Thu, 11 Mar 2021 08:39:11 -0600 Message-Id: <20210311143958.562625-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210311143958.562625-1-richard.henderson@linaro.org> References: <20210311143958.562625-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index c8df45ce28..cfbe039fa6 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -121,16 +121,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_REG_BITS == 64 -/* Read constant (64 bit) from bytecode. */ -static uint64_t tci_read_i64(const uint8_t **tb_ptr) -{ - uint64_t value = *(const uint64_t *)(*tb_ptr); - *tb_ptr += sizeof(value); - return value; -} -#endif - /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -180,6 +170,8 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * tci_args_ * where arguments is a sequence of * + * i = immediate (uint32_t) + * I = immediate (tcg_target_ulong) * r = register * s = signed ldst offset */ @@ -196,6 +188,22 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 = tci_read_r(tb_ptr); } +static void tci_args_ri(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 = tci_read_r(tb_ptr); + *i1 = tci_read_i32(tb_ptr); +} + +#if TCG_TARGET_REG_BITS == 64 +static void tci_args_rI(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 = tci_read_r(tb_ptr); + *i1 = tci_read_i(tb_ptr); +} +#endif + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -481,9 +489,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = regs[r1]; break; case INDEX_op_tci_movi_i32: - t0 = *tb_ptr++; - t1 = tci_read_i32(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_ri(&tb_ptr, &r0, &t1); + regs[r0] = t1; break; /* Load/store operations (32 bit). */ @@ -703,9 +710,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif #if TCG_TARGET_REG_BITS == 64 case INDEX_op_tci_movi_i64: - t0 = *tb_ptr++; - t1 = tci_read_i64(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rI(&tb_ptr, &r0, &t1); + regs[r0] = t1; break; /* Load/store operations (64 bit). */